Integrated Embedded Generic Input Joint Output Controller IEGIJO

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Integrated Embedded Generic Input Joint Output
Controller(IE-GIJO)

• Group 4 Members
• Jay Mayo
• Tony Xinos
• Benjamin Leppard
• Matthew Ludwig

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Problem Description

• Current system used in F/A18 flight simulator
  system uses a serial interface
• Flight simulator system cockpit controls and
  flight instruments are hardwired
• Not all controls and flight instruments are
  connected, reducing effectiveness
• System must be versatile enough to be used for
  other applications
• System should be able to communicate over an
  Ethernet interface

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Our Goals

• Design and build a prototype for demonstration
• Prototype should be capable of handling required
  I/O types
• Prototype should be capable of being connected to
  a network via standard protocols
• Prototype should be reconfigurable and expandable
  to meet changing needs
• Prototype should use open standards to achieve
  interoperability with current and future equipment

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Project Description

• Generic I/O Controller
• Supports Digital I/O, A/D Input, D/A Output,
  Discrete Output, and D/S Output
• Controlled with Ethernet interface via UDP
• Programmable Data Update Rate (1-60Hz)
• Maximum Size of 12 x 12 x 6

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System Specification

• Controlled by an Ethernet connected host computer
  via broadcast UDP/IP
• 128 channels of software controlled Digital Input
  or Output
• 32 channels of 12-bit Analog to Digital
  conversion with software controlled voltage
  ranges
• 32 channels of 12-bit Digital to Analog
  conversion with software controlled voltage
  ranges
• 2 channels of Synchro Outputs
• 16 channels of Discrete Output with software
  controlled voltage
• Software controlled update rate from 1 to 64 Hz
• Unique identifier for each system for use by host
  computer software

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Target System Description

• Two 64-channel digital I/O cards
• One D/S-discrete output card. Two channels of
  D/S, 16 channels discrete output.
• One 32-channel A/D card
• Two 16-channel D/A cards

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System Inputs and Outputs
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System Block Diagram
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Software General Description

• Communicates via UDP/IP and Ethernet with the
  host computer
• Sends the digital I/O and A/D to the host
  computer at the host specified rate
• Updates the digital I/O, D/A, Synchro, and
  Discrete Outputs when supplied values by the host
  computer

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Software Block Diagram
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Hardware Rabbit Core Module

• RabbitCore RCM2200
• 2.3" x 1.6" x 0.86"
• 10Base-T Ethernet
• 128K SRAM
• 256K Flash
• 26 general purpose I/O
• 22.1 MHz clock
• Provides a small, high performance, low cost,
  easily programmable, microcontroller with
  integrated Ethernet

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Software Rabbit Core Module

• Web
• Provide real-time I/O data
• Include basic configurability
• Set Board ID
• Uses the Rabbit provided http server called
  HTTP.LIB
• Ethernet
• Handles all network communications.
• It retrieves an IP address using DHCP
• Actually builds and sends the UDP packets

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Software Rabbit Core Module

• Packet
• This class handles sending and interpreting
  IE-GIJO specific packets
• Stores and retrieves the Board ID
• IO
• Communicates with the Smart Star CPU
• Retrieves the data to be sent back to the Host
  computer
• Send the data received from the Host computer to
  the Smart Star

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Host to GIJO Packet Structure

• Standard Host to GIJO Packet and GIJO to Host
  Packet
• Host to GIJO Packet Types
• PING (0)
• GIJO will respond with its Board ID and MAC
  address in the data field
• SETID (1)
• Set the Machine ID of GIJO. The Board ID is set
  from the Machine ID field
• SENDINFO (2)
• Send to be outputted and configure IO. GIJO will
  respond at intervals specified by the packet

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GIJO to Host Packet Structure

• GIGJO to Host Packet Types
• PINGRESPONSE (0)
• Board ID Machine ID or 0 if not set
• Data MAC Address
• IODATA (1)
• Return gathered data

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RCM to Smart Star communication.

• The Rabbit Core uses a slot on the Smart Star bus
• RCM uses the Smart Star bus for high speed
  (360kbps) asynchronous serial communications
• The communication between the RCM and the Smart
  Start CPU uses a packet protocol

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RCM and Smart Star Communication (contd.)

• Packet
• The same packet structure is used to communicate
  to and from the RCM

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Smart Star
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Software SmartStar CPU

• Basic Smart Star system consists of a backplane,
  5V DC power supply, and CPU card
• Acts as the Communication Link between the Smart
  Star CPU the Rabbit Core Module
• Creates I/O map of cards currently installed on
  the backplane of the Smart Star system
• Determines what type of module is connected to
  the Smart Star (i.e I/O, A/D, D/S)

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Software SmartStar CPU
Rabbit Core Module
SmartStar
Backplane
SmartStar Control Software Manages data
transfer between devices
D I S C R
D I O
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Software Smart Star CPU

• Allows for plug and play capabilities
• Establishes system loops between modules and
  Smart Star CPU card
• Routines were written to service each individual
  card designed in the project
• Software programs and functions for the Smart
  Start are developed using Dynamic C

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Software SmartStar CPU

• Plug and Play Feature
• Creates Ids for each card developed in the
  project
• Gives the smartstar the ability to detect which
  module is plugged into any of its 7 available
  slots
• Allows the user to plug in any module (i.e D I/O,
  Dis.) into any slot, depending on their
  requirements, and establish communication

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Hardware Digital I/O

• 128 channels of digital I/O with the use of two
  cards
• A CPLD 72 macro-cell device to decode bus
  signals. (Xilinx XC9572)
• Digital I/O is programmed for input or output
  and is TTL level 0-5V
• 8 banks of 74ACQ573 Octal latches with 24mA
  sink/source capability.
• 8 Banks of 74HC244 for reading the status of the
  channels if configured for input

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Hardware Digital I/O Block Diagram
Input
CPLD
Smart Star CPU
Output
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Hardware Digital I/O
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Hardware Digital I/OLogic Diagram
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Hardware Digital I/O Board Design
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Functional Digital I/O Prototype
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Hardware D/S ConversionRequirements

• Two channels of synchro stator output at 11.8V
  L-L (standard for aircraft applications). Used
  for flight instruments on F/A-18 simulator
• Converter must be able to operate with 60 Hz and
  400 Hz power (standard for aircraft applications)
• Converter must supply enough VA to drive multiple
  CT, CDX, and TR loads

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Hardware D/S ConversionRequirements (cont.)

• Stator output can be stepped up or converted to
  resolver format. Rotor voltages can be
  controlled by software
• Converter must have sufficient resolution (to
  0.01 degrees) with good accuracy
• Converter must interface to 8-bit data bus

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Hardware D/S ConversionDSC-10510

• DSC-10510 is built by Data Device Corp
• 11.8 V L-L, 0.7A (0.8A kick for TR loads), 7 VA
  output
• Transparent double-buffered latches enable
  interfacing to 8-bit data bus
• Built-In Test (BIT) is included to signal
  over-current, over-temperature, loss of reference
  conditions in converter
• 16-bit resolution offers accuracy to 2 minutes
• Use of pulsating power supply reduces power
  dissipation by half compared to using regulated
  supplies
• External transformers can be used with this
  component to step up stator output to 90 V L-L,
  or to convert to resolver format signals

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Hardware D/S ConversionDSC-10510 Block Diagram
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Hardware D/S ConversionSchematic
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Hardware D/S ConversionShutdown Scheme

• Two shutdown scenarios for D/S Converters
• Deliberate Shutdown If BIT?0 and EN1, power
  output stages on both converters are shut down,
  along with rotors (if present)
• Over-temperature Shutdown If BIT?0 and EN0,
  shut down entire D/S circuit, alert operator

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Hardware D/S Converter Implementation Issues

• D/S converter system is generic, not designed for
  any one particular load. Load tuning must be
  done externally based on the connected load
  impedances, especially for loads connected in
  parallel
• Power amplification stages on the D/S chips will
  be using an unregulated power supply, to reduce
  overall power dissipation

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Hardware D/S ConversionImplementation Issues
(cont.)

• Reference transformer for D/S power system may
  need to be custom-built to handle both operating
  frequencies, and may be too large to fit on the
  D/S card, requiring the power supply and
  frequency selection circuitry to be moved
  off-board
• A staggered startup scheme for multiple D/S cards
  can be done to avoid overloading power supplies
  at system startup
• Power supply problems may arise if multiple D/S
  cards are placed in system, due to power demand

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Hardware Discrete Outputs

• 16 channels of discrete output digitally
  selectable between 0V, 15V, and 28V sourcing at
  least 20 mA
• 4 8-bit registers will be used to select the
  appropriate level of discrete output
• An adjustable regulator will supply the output
  voltage to the discrete channels

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Discrete Output Schematic
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Discrete Output Logic Diagram
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Synchro/Discrete Output Board Design
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Functioning Discrete Out Prototype
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Hardware A/D Conversion

• 32 channels of A/D at 12 bits of accuracy
• Accomplished with 2 ADS7805 16-bit converters
• Differential measurement to provide theoretical
  305uV of accuracy
• Signal conditioning to scale measurement to range
  of converter (10V input)

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A/D Block Diagram
Differential Input
Smart Star CPU
CPLD
Mux Selection
Amplification and Signal Conditioning
Conversion
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A/D Schematic
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A/D Logic Diagram
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A/D Board Design
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Analog Input Prototype
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Hardware D/A Conversion

• 32 channels of D/A conversion at 12 bits of
  accuracy
• Accomplished with 8 banks of DAC7614U converters
  
• 4 channel voltage out four quadrant multiplying
  DAC
• Signal conditioning on all outputs to provide
  complete range of voltages

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Hardware D/A Conversion

• 10uS settling time to 0.012
• Serial 16 bit input
• Resettable to mid-scale value (0V for bipolar
  operation)
• Requires 5V supplies and 2.500 and 2.500
  references

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D/A Block Diagram
Smart Star CPU
CPLD
Conversion X 8 Banks
Output Channels
Gain Setting 4 per Channel
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D/A Schematic
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D/A Board Design
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Administrative Metrics

• Design is comprised of over 63 unique parts, and
  over 1231 individual components.
• 4 Multi-layer boards designed, with a total of
  703 nets, 2155 connections, and over 147 feet of
  routing.
• Over 1200 man hours in research, design, coding,
  and PCB assembly
• Total system cost to date 3,613.59

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Administrative Milestone Chart
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Administrative Project BOM
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Potential Applications/Future Uses

• Simulation systems
• Data acquisition systems
• Industrial control applications
• Automated testing equipment
• Internet enabled autonomous device
• Networked expandable I/O