Microprogram

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Microprogram

• Anselmo Lastra

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Topics

• Microprogrammed CPU
• Pipelining
• Review of Ch. 4-5

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Recall Multi-Cycle CPU

• Microprogram word
• Right side has control signals
• Left has sequencing signals

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Block Diagram
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Writing program

• First look at ASM chart
• These are simple instructions
• Add Immediate, Load, Store
• Look at one in detail

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Add Immediate

• First, state IF instruction fetch, loads IR from
  memory, increments PC

• Second, state EX0 load the current address
  register (CAR)
• CAR now the opcode
• Next state will be opcode of instruction

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Now Execute ADI

• Now add the 3 immed. bits to SA and load to RD
• Then go to next inst. fetch

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Opcodes

• It doesnt matter what opcodes are assigned to
  which operation
• All they do is select a microprogram memory
  location

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Microprogram for ADI

• IF
• EX0 always follows
• EX0 is NXT ADD, but MS is told to CNT
• So EX0 better be right after IF
• IL is loading the instruction register
• PI is incrementing the PC
• PL says not to load PC
• MW/RW says dont write memory or registers
• MM says address memory from the PC

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Next microinstruction, EX0

• EX0
• MC is selecting the Opcode (OPC) as next
  microinstruction
• IR and PC not loaded, PC not incremented

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Now the Actual Work

• ADI
• MC gates next address (NA) field
• NA is IF (to load IR with next instruction)
• Other signals are datapath
• TD/TA - enable actual registers (instead of
  temps)
• MB Gate constant
• FS is add
• RW - Write to register

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Timing

• Each instruction takes 3 cycles
• However, cycle length is shorter
• Because paths are broken up
• Weve added new registers, so that consumes time
• Overall time probably longer
• However,
• Can add complex instructions
• Can pipeline

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Multi-Cycle Instructions

• First look at Load Register Indirect
• LRI, opcode 110
• Uses indirect addressing (a pointer stored in
  memory)
• RDR lt- MMRSA
• Contents of register SA addresses word in memory
  that is address of word to be stored in register
  DR

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ASM

• Incoming branch from EX0
• LRI has two states but no decision
• LRI0 addr in first location MRSA stored in
  temporary
• Used in LRI1
• Four cycles
• Alternative is two LD operations

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Multicycle with Decision

• Shift Right Multiple (SRM)
• Shift SA right OP positions and store in DR
• SA must be equal to DR
• Odd and mandated by hdw design

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SRM

• R8 stores num shifts
• First tested for zero shifts
• Then right shifted one bit
• R8 decremented and tested

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Cost

• Takes 2s 3 cycles, where s is number of shifts
• Alternative is a one-bit shift instruction
  executed s times would take 3s instructions
• Break even point is 3-bit shift

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Multicycle can be Hardwired

• I expect youll do so for MIPS
• Just like multiplier
• Can use a sequencer and decoder
• Or a flip-flop per state
• Can use counter (or shift register) as sequence
  register
• Next sequencer using counter with reset

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Hardwired Sequencer

• Left decoder might get large for many
  instructions
• Can incorporate into control
• Counter sequences states until it is reset

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ASM

• Note that most instructions only 2 cycles
• Because no CAR
• LRI takes 3 cycles because of indirection
• Combinational logic for control signals

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Control Signals

• Basically write logic equations for control
  signals
• CR reset for sequence counter
• IF code is 0, which always runs first
• Return to IF by resetting counter
• For simple instructions, reset after EX0, so
• LRI needs the EX1 cycle

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Control Signals

• You can imagine that it would not be hard to code
  this in Verilog
• Remember that the control logic will actually be
  in memory, not gates

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Advantages/Disadvantages

• Hardwired better for simple systems
• Microprogrammed enables easier implementation of
  complex instructions
• Can make system faster with pipelining

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Pipelined Control

• Recall
• Break system up into parts
• Insert registers between parts
• Multiple instructions being executed at a time
• Lets look at block diagram

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Pipelined Computer

• Stages
• Instruction fetch
• Decode
• Execute
• Write Back
• PC update is complicated

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Pipelined Execution

• Remember that pipeline fill and empty will lower
  performance

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Review Chs. 4, 5

• Chapter 4
• Latches and Flip-Flops introduced
• State tables and diagrams
• New Verilog to express sequential circuits

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Latches and Flip-Flops

• You already know a lot about basic types
• And its open book
• Not much to say here

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State Tables

• Allow you to specify (or analyze) behavior of
  sequential system
• Example next

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Example from Fig. 4-18
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State Table
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Sequential Circuit Types

• Moore model outputs depend on states

• Mealy model also depend on inputs

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Verilog

• The reg data type
• The always block
• And posedge/negedge
• The case statement
• Know how to implement a state table in Verilog
• Like the lock
• Book has two-stage state sequencing

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My Lock Code

• Theres a module that instantiates
• Header
• module lock(C, Button, Data, Reset, Open, state)
• input C
• input Button
• input 30 Data
• input Reset
• output Open
• output 20 state // Output for debugging
• reg 20 state // Just one state register

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Sequencing

• always _at_(posedge C or posedge Reset)
• begin
• if (Reset)
• state 0
• else
• case ( state )
• 0 if(Button 1 Data 1) state 1
  else state 0
• 1 if(Button 0) state 2
• 2 if(Button 1)
• if(Data 2) state 3 else state 0
• else
• state 2
• 3 if(Button 0) state 4
• 4 if(Button 1)
• if(Data 3) state 5 else state 0
• 5 state 5
• endcase
• end

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Chapter 5

• Registers
• How to implement in Verilog
• Shift Registers
• What they do
• How to implement in Verilog
• Counters
• Verilog for counter
• Counter with parallel load
• Counter with reset

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Verilog for Shift Register

• module srg_4_r_v (CLK, RESET, SI, Q,SO)
• input CLK, RESET, SI
• output 30 Q
• output SO
• reg 30 Q
• assign SO Q3
• always_at_(posedge CLK or posedge RESET)
• begin
• if (RESET)
• Q lt 4'b0000
• else
• Q lt Q20, SI
• end
• endmodule

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Verilog Counter

• module count_4_r_v (CLK, RESET, EN, Q, CO)
• input CLK, RESET, EN
• output 30 Q
• output CO
• reg 30 Q
• assign CO (count 4'b1111 EN 1b1) ? 1
  0
• always_at_(posedge CLK or posedge RESET)
• begin
• if (RESET)
• Q lt 4'b0000
• else if (EN)
• Q lt Q 4'b0001
• end
• endmodule

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Today

• Looked at microprogramming CPU
• Pipelining
• Review for next Tuesdays quiz
• Reminder No class next Thurs.