COE 308: Computer Architecture T041 Dr' Marwan AbuAmara

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COE 308 Computer Architecture (T041)Dr. Marwan
Abu-Amara

• Chapter 2 Instruction Set Design (cont.)

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Internal Operation
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Internal Operation (cont.)

• Register Transfer Notation is used to show the
  internal transfers
• RA ? RB transfer contents of RB to RA
• Note that a direct path must exist between RA and
  RB. Thus, the following is the accurate Register
  Transfer Notation
• ALUo/p ? RB
• RA ? ALUo/p
• However, we will not show the intermediate steps
  (i.e. well use RA ? RB)

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Fetch Cycle

• MAR ? PC set mem. addr. to contents of PC
• IR ? MDR instr. is in MDR ? transfer to IR
• PC ? PC 4 increment PC to point to next
  instr.
• OR
• MAR ? PC
• IR ? MDR PC ? PC 4 simultaneous actions
• Fetch cycle of instruction is independent of type
  of instruction, and steps are always the same
• Can implement by hardwired logic

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Execute Cycle

• A ? Rs1
• B ? Rs2
• No need to perform a decode to execute the steps
  above for all types of instructions (taking
  advantage of the instruction format)
• If theres an instruction that doesnt use any of
  the operands, then its OK! (can throw away the
  contents of A B !)
• The steps for the Fetch cycle and the Execute
  cycle will precede the steps needed for the
  different classes of instructions

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ALU Instruction (R-R-R) (R-R-I)

• R-R-R
• S1 bus ? A S2 bus ? B
• D bus ? S1 bus ltoperationgt S2 bus
• C ? D bus
• Rd ? C
• R-R-I
• S1 bus ? A S2 bus ? IR15-0
• D bus ? S1 bus ltoperationgt S2 bus
• C ? D bus
• Rd ? C

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Memory Reference (LD/ST)

• LD
• MAR ? A IR15-0
• C ? MDR
• Rd ? C
• ST
• C ? Rd
• MAR ? A IR15-0
• MDR ? C
• However, C is not connected to Register File as a
  read register! ? Wait until instruction is
  decoded and then use B to hold contents of Rd

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Memory Reference (cont.) Branch

• ST
• B ? Rd
• MAR ? A IR15-0
• MDR ? B
• Branch
• condition ? A ltoperationgt B
• ALUo/p ? PC IR15-0
• IF (condition TRUE) then PC ? ALUo/p

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Jump

• Jump (PC-relative addressing Jump)
• PC ? PC IR25-0
• Jump (Register-indirect addressing Jump)
• PC ? A IR15-0
• JAL
• R31 ? PC
• PC ? PC IR25-0

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Centralized Control Unit Design

• 2 approaches
• Hardwired Logic Design
• Each step or group of steps that can be performed
  simultaneously is a state of the machine ? State
  diagram

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Centralized Control Unit Design (cont.)

• An n to 2n decoder is used to decode the
  instructions opcode ? 6-to-64 decoder is needed
  for our processor
• Each state requires specific signals to be
  generated. For example, to transfer contents of
  one register to another we need a signal to cause
  contents of the source register to be loaded onto
  a bus, and a signal to cause the contents of the
  bus to be loaded into the destination register
• Very hard to implement and to debug
• Microprogramming
• Operations for each state are encoded in binary
  as a microinstruction and is stored in a
  microprogram memory
• Each microinstruction will cause the signals
  necessary to transfer data from one place to
  another in the processor, and activates the ALU
  and other function units if necessary

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Centralized Control Unit Design (cont.)

• Each machine instruction is translated into a
  microprogram consisting of several
  microinstructions
• Microprograms for all machine instructions are
  stored in a microprogram memory

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Centralized Control Unit Design (cont.)
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Centralized Control Unit Design (cont.)

• Example

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Centralized Control Unit Design (cont.)

• Solution