NAND Implementation

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NAND Implementation

• ICS 30/CS 30

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NAND and NOR IMPLEMENTATION Digital circuits are
more frequently constructed with NAND or NOR
gates than with AND and OR gates. NAND and NOR
gates are easier to fabricate w/ electronic
components and are the basic gates used in all IC
digital logic families. Because of the prominence
of NAND and NOR gates in the design of digital
circuits, rules and procedures have been
developed for the conversion from Boolean
functions given in terms of AND, OR, and NOT into
equivalent
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NAND Implementation
NAND and NOR IMPLEMENTATION NAND or NOR logic
diagrams. To facilitate the conversion to NAND
and NOR logic, it is convenient to define two
other graphic symbols for these gates.
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NAND and NOR IMPLEMENTATION
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NAND and NOR IMPLEMENTATION Similarly, there are
two graphic symbols for the NOR gate.
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NAND and NOR IMPLEMENTATION
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NAND and NOR IMPLEMENTATION A one-input NAND or
NOR gate behaves like an inverter. As a
consequence, an inverter can be drawn in three
different ways. The small circles in all inverter
symbols can be transferred to the input terminal
w/o changing the logic of the gate. It should be
pointed out that the alternate symbols for the
NAND and NOR gate could be drawn w/ small
triangles in all input terminals instead of the
circles. A small triangle is a negative-logic
polarity
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NAND Implementation
NAND and NOR IMPLEMENTATION indicator. W/ small
triangles in the input terminals, the graphic
symbol denotes a negative-logic polarity for the
inputs, but the output of the gate(not having a
triangle) would have a positive-logic assignment.
Well stay w/ positive logic throughout and
employ small circles when necessary to denote
complementation.
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NAND and NOR IMPLEMENTATION
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NAND and NOR IMPLEMENTATION
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NAND and NOR IMPLEMENTATION
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• NAND Implementation
• The rule for obtaining the NAND logic diagram
  from a Boolean function is as follows
• Simplify the function and express it in sum of
  products(SOP).
• Draw a NAND gate for each product term of the
  function that has at least two literals. The
  inputs to each NAND gate are the literals of the
  term. This constitutes a group of first-level
  gates.

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NAND Implementation
NAND Implementation 3. Draw a single NAND gate
(using the AND-invert or invert-OR graphic
symbol) in the second level, w/ inputs coming
from outputs of first-level gates. 4. A term w/ a
single literal requires an inverter in the first
level or may be complemented and applied as an
input to the second-level NAND gate.
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NAND Implementation
NAND Implementation Before applying these rules
to a specific example, it should be mentioned
that there is a second way to implement a Boolean
function w/ NAND gates. Remember that if we
combine the 0s in a map, we obtain the
simplified expression of the complement of the
function in SOP. The complement of the function
can then be implemented w/ two levels of NAND
gates using the rules stated. If the normal
output is desired, it would be
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NAND Implementation necessary to insert a
one-input NAND or inverter gate to generate the
true value of the output variable.
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NAND Implementation
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NAND Implementation