Implementation of Nonrestoring Array Divider

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Implementation of Non-restoring Array Divider

• Wei Jiang
• ECE651
• Fall, 2003

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Division operation
Repeated shift and subtracts
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Basic Divider Cell
Previous Stage Partial Remainder
d
Previous Stage Quotient
Cout
FA
Cin
Partial Remainder
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Remainder Correction

• The remainder output is not the real remainder.
• Depends on the last bit of the quotient
• If Qn1, the remainder output is correct
• If Qn0, the output is the real remainder
  subtracted by divisor Add divisor back to
  correct the remainder.

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Remainder Correction Cell
Last Stage Partial Remainder
d
Last Stage
Cout
FA
Cin
Real Remainder
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Divider Cell FET level schematic
51 FETS in total
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Pre-Layout Simulation
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Prolific Layout (76 lambda with folding)
132 micron
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Prolific Post-layout Simulation
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Manual Standard CellGates Arrangement

• Gate Level schematics in HW3 (with an extra XOR
  gate)

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Gates Arrangement

• 2 XORs on the sides (Also for convenience of next
  part of the project)
• Tried to minimize the wire routing
• Tried to maximize the overlapping of the
  transistors

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1 bit Standard Cell Layout

• 74.4 micron - Competitive to prolific layout (132
  micron with folding)

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1 bit Standard Cell Post Layout
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Bit Slice Cell

• Divide gates into 3 parts
• Fold the standard cell gates arrangement
• Easy routing since most of wires are connecting
  to the close neighbors.

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1 Bit Slice layout
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1 Bit Slice Post Layout
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Comparison

• Area Delay. Developing Time

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1 Bit RC Standard Cell Layout
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RC standard cell post layout
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1 Bit Datapath RC Cell Layout
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RC Data Path Post Layout
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8-bit schematics
1100 FETS
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8-bit datapath layout
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8-bit datapath post-layout
1100000/10011010, Remainder 0110
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8-bit layout by SE
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8-bit Standard cell post-layout
1100000/10011010, Remainder 0110
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Conclusion

• Regular Structure
• Use shortest wire connecting to the neighbors
• Efficient and easy to be implemented by VLSI
• Can be efficiently pipelined