Chapter 3 The Digital Logic Level

1
Chapter 3The Digital Logic Level

• CS 271 Computer Architecture
• Indiana University Purdue University Fort Wayne
• Mark Temte

2
Some electrical science

• If resistance R2 is large, then Vout is nearly
  Vcc volts
• If resistance R2 is small, then Vout is nearly 0
  volts
• Let Vcc be about 5 volts
• Think of 0 to 1 volts as representing a binary
  0
• Think of 2 to Vcc volts as representing a binary
  1

R1
R2 R1 R2
Vcc
R2
ground

• Then Vcc represents 1 and ground represents
  0

3
Transistors

• The transistor was invented at Bell Labs in 1948
  by John Bardeen, Walter Brattain, and William
  Shockley
• They were awarded the Nobel Prize in physics for
  this discovery in 1956
• The transistor
• revolutionized computer
• hardware by the late
• 1950s, making vacuum
• tubes obsolete

bipolar transistor
4
Transistors

• Suppose we replace resistor R2 in the earlier
  diagram by a transistor
• Basic rules for transistors
• If the base is high with respect to the emitter,
  then there is essentially no resistance between
  the collector and the emitter
• If the base is low, then there is high resistance

• Therefore, . . .
• Vin binary 1 implies that Vout binary 0
• Vin binary 0 implies that Vout binary 1
  

5
Transistors

• This circuit is an inverter (also called a NOT
  gate)
• An inverter complements input
• Changes 0 to 1 and changes 1 to 0
• A logic icon and a truth table
• for an inverter are given at right
• We represent the complement of
• a Boolean value A by A
• When Vin changes, the time that
• Vout takes to transition is a few
• nanoseconds (10-9 seconds)

inversion bubble
6
NOR gate

• Output 1 if and only if A 0 and B 0
• (an inverted OR gate)

NOR implementation
NOR icon and truth table
7
The AND gate and OR gate

• Represent
• A OR B
• by A B
• Represent
• A AND B
• by AB

8
NAND gate

• Output 0 if and only if
• A 1 and B 1
• (an inverted AND gate)

9
Synthesis

• All gates can be synthesized using only NOR gates
• This can be also done using only NAND gates

AND gate
inverter
OR gate
10
Why bother with OR gates?

• Why not just use the following?

A A B B

• Problem
• Output is OK, but voltage on A causes voltage
  on B

11
Multiple input gates

• 3 input AND
• 4 input OR

A B C
A B C
ABC
ABC
A B C D
A B C D
ABCD
ABCD
12
Boolean functions

• Imagine a black box f
• Any number of Boolean inputs are permitted
• The single output is a Boolean value
• The output is a function of the inputs
• The gates we just looked at are examples of
  Boolean functions

A B C
f
f(A,B,C)
13
Boolean function behavior

• The behavior of a Boolean function can be
  specified by a truth table

Rows should be listed in in base-2 numerical
order For n inputs, there are 2n rows
14
Synthesis of Boolean functions

• An arbitrary Boolean function can be easily
  synthesized using multiple-input AND gates, OR
  gates, and inverters
• This requires one AND gate for each combination
  of inputs that results in a 1
• Synthesis method appearing on the following slide
  uses more inverters than the method indicated in
  the text but is easier to draw

15
Synthesis example (for f defined earlier)
A B C






f(A,B,C)






16
The eXclusive OR gate (XOR)
The icon for an XOR gate is given at right
17
Boolean algebra

• First used by English mathematician George Boole
  (1815 1864)
• A Boolean expression giving the Boolean function
  f defined earlier is

f(A,B,C) ABC ABC ABC ABC
18
Boolean algebra

• Boolean identities may be used to simplify
  Boolean expressions

19
Boolean algebra

• De Morgans laws
• not( A and B ) not( A ) or not( B )
• not( A or B ) not( A ) and not( B )
• Example
• I will buy a new CD if (A) I have enough cash and
  (B) it is in stock
• I wont buy a new CD if (A) I dont have enough
  cash or (B) it is not in stock

20
Boolean algebra

• Distributive laws
• A(B C) AB AC
• A BC (A B)(A C)
• Idempotent laws
• AA A
• A A A
• Note Each law has a dual form
• Swap and with or and 0 with 1

21
Simplification example

• Simplify the function f defined earlier

f(A,B,C) ABC ABC ABC ABC AB(C C)
(A A)BC AB BC
A B C


f(A,B,C)


22
Simplification

• The goal of simplification is to minimize the
  total number of gates used in building a given
  Boolean function
• This is not our goal this semester
• Just interested in demonstrating feasibility

23
Major types of gate technology

• Bipolar
• TTL
• Transistor-Transistor Logic
• ECL
• Emitter-Coupled Logic
• Ten times as fast as TTL
• MOS
• Metal Oxide Semiconductor
• One tenth as fast as TTL
• Small
• Low power

24
IC chips

• Gates are configured on integrated circuit (IC)
  chips
• SSI (Small Scale Integration)
• 1 to 10 gates on a chip
• MSI (Medium Scale Integration)
• 10 t0 100
• LSI (Large Scale Integration)
• 100 to 100,000 gates
• VLSI(Very Large Scale Integration)
• greater than 100,000 gates
• Today there can be 100,000,000 gates

25
Typical SSI chip Dual Inline Package (DIP)

• Pins for power (Vcc), ground, inputs, and outputs

26
Connections

• This DIP is suitable for applications in which
  individual gates are needed
• For larger applications, the gates need to be
  connected internally during manufacture
• Connecting large numbers of gates externally is
  not practical
• Too many pins
• See remark on on page 129 of the text concerning
  gate-to-pin ratio for a chip with 10 million
  transistors

27
Combinational logic circuits

• These may have many inputs and/or outputs
• Each output is a Boolean function of the inputs
• No internal memory
• Examples
• Multiplexer
• Demultiplexer
• Decoder
• Comparator
• Arithmetic unit

28
Multiplexer

• This circuit contains
• 2n input lines
• n control lines
• One output line
• The control lines select one of the inputs and
  gate it to output

n 3 in this example
29
Multiplexerimplementation
Exactly one AND gate is enabled at a
time Application Parallel-to-serial converter
for sending data over a modom
30
Demultiplexer

• Routes input to selected output

D0




D1



D2


D3
A B
31
Decoder

• Raises one of 2n
• output lines in
• response to an
• n-bit binary input
• value
• See if you can
• simplify this diagram
• by using more
• inverters

32
Other combinational logic circuits

• Comparators
• Read pages 149 150
• Programmable logic arrays (PLAs)
• Read pages 150 152

33
Arithmetic circuits

• Shifter
• Ripple carry adder
• Constructed from full-adders
• Full adders are constructed from two half-adders
• ALU

34
Zero-fill shifter
Set C 1 to shift right and C 0 to shift left
35
Ripple carry adder

• Adds two n-bit twos complement words A and B
• Let Ai be the ith bit position of A, and
  similarly for B
• Output is the sum S of A and B together with
  overflow bit V

s0
s1
s2
s13
s14
v s15
c13
c14
c0
c1
c2
c12
A
A
A
A
AV
½A

A0 B0
A1 B1
A2 B2
A13 B13
A14 B14
A15 B15
36
Half-adder
si
ci
½A
Ai Bi
37
Full adder
si
Ci-1
ci
A
Ai Bi
38
Full adder with overflow
v s15
C14
AV
A15 B15
See if you can implement this with two half
adders, two 3-input AND gates, inverters, and a
2-input OR gate
39
Recall twos complement addition

• In the first addition, there is a carry out of
  the leftmost bit position (throw it), but no
  overflow
• In the second addition, there is no carry out of
  the leftmost bit position, but there is overflow

0 1 1 0 1 0 1 1 2 1 1 0 0 0 0 1 1 2
0 0 1 0 1 1 1 0 2
0 1 1 0 1 0 1 1 2 0 1 0 0 0 0 1 1 2
1 0 1 0 1 1 1 0 2
40
ALU

• An n-bit
• ALU is built
• from n
• 1-bit
• ALUs

41
ALU

• This ALU contains a two-bit decoder for the
  op-code given by F0 and F1
• The meaning is given by
• The decoder raises the enable line associated
  with the op-code

42
An n-bit ALU
43
Clock

• A device that delives voltage pulses at regular
  intervals
• Clock frequency
• 4.77 MHz original IBM PC (1979)
• 3000 MHz today
• 1 MHz 1 million cycles per second
• 1000 MHz 1 pulse per nanosecond (10-9 sec)

voltage
5
time
0
44
Memory

• A latch is a 1-bit memory
• Latch output Q remembers if the most recent input
  voltage was on S (Q 1) or was on R (Q 0)
• S stands for Set
• R stands for Reset
• Q is often available instead of or in addition to
  Q

Q
S
R
Q
SR-latch
45
Latch implementation with NOR gates
46
Clocked latches

• Inputs apply only when a clock input line CK
  has voltage
• CK is also call enable or strobe
• Clock input may not actually be attached to a
  clock
• Clocked SR-latch
• A voltage pulse on CK gates R or S into an
  SR-latch
• Clocked D-latch
• A voltage pulse on CK causes latch output Q to
  remember the value on input D at the time of the
  pulse

47
Clocked SR-latch and clocked D-latch
48
Flip-flops

• A latch is level-triggered, whereas a flip-flop
  is edge-triggered
• This means that the state transition in a
  flip-flop does not occur when the clock is 1
• Instead, it occurs during the transition from 0
  to 1 (triggered by the rising or leading edge of
  the pulse)
• The length of the clock pulse is not important

49
Flip-flops

• Some flip-flops transition during a transition
  from 1 to 0 (trailing-edge-triggered)

leading-edge-triggered flip-flop
trailing-edge-triggered flip-flop
50
Assertion and negation

• Sometimes voltage on a pin (voltage high) causes
  an action to happen
• Sometimes the action is caused by withdrawing
  voltage (voltage low)
• To avoid confusion, we say that a signal is
  asserted to mean it causes some action
• When a pin is asserted low, its name often has an
  overbar, as in OE
• The opposite of asserted is negated (nothing
  special happens)

51
Registers

• Flip-flops are grouped together to form registers
• Example (next slide)
• This is a 8-bit, 20-pin register
• Asserting pin 1 clears all flip-flops
• Asserting CLR on a flip-flop clears the flip-flop
• Voltage on pin 11 loads all 8 flip-flops by
  reading the D-inputs from appropriate pins
• The inverter serves as an amplifier to drive the
  8 CK lines

52
Register example
53
Tri-state devices

• These are like inverters, but a third line
  disconnects output from a circuit
• This causes output to float
• More specifically, these are called noninverting
  buffers or inverting buffers
• These are needed in order to disconnect lines
  from a bus

54
Memory

• The example of a memory on the next slide
  involves
• 4 words with 3 bits per word
• Two address input lines A1 and A0
• Data input lines I2, I1, and I0
• Control lines
• CS Chip Select
• RD ReaD / write
• OE Output Enable
• Output lines O2, O1, and O0
• To read, assert CS, RD, and OE
• To write, assert CS and negate RD and OE

55
Memory example
MBR
I2 I1 I0 A1 A0 CS RD OE
O2 O1 O0


memory

MAR






bus
56
A four word memory
57
Memory design easily extends

• A 512K x 8-bit memory requires . . .
• 19 address lines
• (219 512K)
• 8 input lines
• 8 output lines
• CS, RD, OE, power, and ground

58
Current memory

• Available today
• 512 MB 64M x 64-bit SDRAM
• 333 MHz (3 nsec)
• under 100
• See www6.tomshardware.com

59
RAM varieties

• Static RAM (SRAM)
• D-flip-flops
• Fast for cache
• Dynamic RAM (DRAM)
• Inexpensive and high density for main memory
• Implemented with capacitors (must refresh every
  few msec)
• EDO DRAM
• Extended Data Output
• Asynchronous (uses pipelining)

60
RAM varieties

• Synchronous DRAM
• SDRAM
• Hybrid of static and dynamic RAM
• Single clock for data and address lines
• No need for extra control signals needed with
  asynchronous memory
• Double Data Rate SDRAM
• DDR
• Chip produces output on both the rising edge of
  the clock and the falling edge

61
Other types of memory

• ROM
• Read-Only Memory
• PROM
• Programmable Read-Only Memory
• EPROM
• Erasable Programmable Read-Only Memory
• EEPROM
• Electronically Erasable PROM
• Flash memory
• 10,000 erasures
• Digital cameras, USB memory sticks, PDAs

62
Computer system

• A computer system typically consists of . . .
• Memory
• Microprocessor
• Buses
• I/O devices
• We have studied how to build a memory
• We will look at the other three in turn . . .
• Then put them together into a complete computer
  system

63
Microprocessor

• A microprocessor
• is a CPU on
• a chip
• Also called a
• processor
• The pinout is
• what the
• signals on
• the various
• pins mean

64
Microprocessor

• A specific microprocessor is the Zilog Z80
• Control pins include bus control, interrupts, bus
  arbitration, coprocessor, status, and
  miscellaneous
• Microprocessor design will be the focus of
  Chapter 4

Z80
13
16
control
address
8
data
clock 5v ground
65
Buses

• Physically, a bus is just parallel wires
• Rules
• A device may listen anytime
• A device normally floats output to the bus
  except when it talks to the bus
• A tri-state device is used to float output
• A device must own the bus to talk

bus
device
16
16
In
Out
66
Bus exampleGating a 3-bit register to a bus
3
3
SEND_A
In
out
register
LOAD_A
?
?
?
?
?
?
?
?
?
SEND_A
?
?
?
D Q gt
D Q gt
D Q gt
LOAD_A
?
?
?
67
Bus issues

• Bus protocol
• Rules for using the bus
• All devices must obey these rules
• In addition, there are mechanical and electrical
  specifications
• Master / slave devices
• Masters initiate transfers
• The CPU for example
• Slaves must wait for requests
• Memory for example
• A disk controller is both a master and a slave at
  different times

68
Bus issues

• Bus width
• Number of lines
• Affects bandwidth
• Multiplexed bus
• A given line is used for different purposes at
  different times
• Increases value of existing lines

69
Bus issues

• Synchronous bus
• Clock driven
• Typically 5 to 333 MHz
• Each clock pulse defines a bus cycle
• Example
• See next slide and text pages 180 182
• Three bus cycles needed for the CPU to read a
  byte from memory
• Note the wait state
• Wait states are extra bus cycles that need to be
  added if a slave device is slower than the master
• All bus activity and timing must be exactly
  defined

70
(No Transcript)
71
Bus issues

• Asynchronous bus
• No master clock
• Each master / slave pair use the bus just as long
  as necessary
• Full handshake needed
• A full handshake is timing independent
• Example of master reading from a slave
  asynchronously
• Master asserts MSYN command
• Slave asserts SSYN slave sending
• Master negates MSYN data captured
• Slave negates SSYN bus free
• Here . . .
• MSYN Master SYNchronization
• SSYN Slave SYNchronization

72
Bus issues

• Bus arbitration
• Needed when several devices want to become bus
  master at the same time
• Sometimes built into CPU chip
• Example centralized arbitration using daisy
  chaining

Note there should be OR gates along the bus
request line
73
Centralized arbitration

• When the arbiter sees a request, it asserts the
  grant line if the bus is free
• When a device receives a grant . . .
• if it needs the bus, it then has the right to
  talk to the bus
• otherwise, it passes the grant to the next device
• The daisy chaining scheme has implicit
  priorities
• When there is no special memory bus, the CPU
  usually has the lowest priority

74
Centralized arbitration

• Priorities may be more explicit by having several
  such systems
• Each device is has a defined priority and
  requests the bus on a separate system for that
  priority

75
Arbitration for interrupts

• Multiple interrupts may occur simultaneously
• Arbitration with priorities is needed
• Example
• Intel 8259A interrupt controller

76
Intel 8259A interrupt controller

• Used with Intel PCs
• Any IRQ causes 8259A to assert INT
• CPU asserts INTA (INTerrupt Acknowledge)
• 8259A then puts the number of the highest
  priority IRQ on the data bus D0 D7
• CPU uses this number as an index into a table of
  addresses
• This table is called an interrupt vector
• The address from the table is the start of an
  interrupt handler method

77
Example CPU chips

• Intel 8088
• Original IBM PC processor
• 29K transistors
• 16-bit internal data path
• 8-bit external data path
• 40 pins
• 20 bit addresses
• 1 MB maximum addressable bytes
• Only 640KB were available to DOS programs

78
Example CPU chips

• Intel 80286
• 68 pins
• 16 MB maximum addressable bytes
• Intel 80386
• 132 pins
• 32-bits internal and external data paths
• 4 GB maximum addressable bytes
• Intel 80486
• Coprocessor on chip
• Cache in chip

79
Example CPU chips

• Successive Intel processors
• Pentium
• Pentium pro
• Pentium II
• Pentium III
• Pentium 4
• Focus on this on next slide
• Itanium
• Different architecture
• 64-bit data path

80
Example CPU chips

• Pentium 4
• Recent version
• 55 M transistors
• 3.2 GHz
• 0.09 micron line width ( 90 nanometers)
• 64 GB address space
• 36-bit addresses
• Only 33 address pins needed
• All memory transfers are 8-byte (64-bit)
  transfers
• All addresses are aligned on locations divisible
  by 8
• Low-order 3 bits are always 0

81
Example CPU chips

• Pentium 4
• Superscalar architecture
• Hyperthreaded
• two sets of registers allowing rapid switch
  between programs
• Caches
• 8 KB level 1 cache (internal) for instructions
• Fetched Instructions are converted to
  microinstructions for RISC core
• 1 MB level 2 cache (internal)
• Both instructions and data
• 2 MB level 3 cache (Extreme Edition)
• Performs snoop on memory bus in multiprocessor
  systems to maintain cache consistency

82
Example CPU chips

• Pentium 4
• Separate memory and PCI buses
• 478 pins (85 power, 180 ground,198 signal,15
  spare)
• 63-82 watts !

83
The Pentium 4s logical pinout
84

• Pipelining requests on the Pentium 4s memory
  bus
• The pins on the left side of the pinout (previous
  slide) control memory bus operations

85
Example CPU chips

• UltraSparc III
• 64-bit addresses
• RISC architecture
• Designed for large, shared-memory multiprocessor
  serves
• 29 M transistors, 1.2 GHz, 0.13 micron lines
  width, 50 watts
• Can issue 4 instructions per clock cycle
• Equivalent to a single-issue CPU _at_ 4.8 GHz
• Six internal pipelines (two, with 14 stages, for
  integer operations)

86
Example CPU chips

• UltraSparc III
• 1368 pins, 128-bit data bus, 43-bit address for 8
  TB of memory
• Split internal level 1 caches
• 32 KB for instructions
• 64 KB for data
• External level 2 cache
• 1 MB to 8 MB

87
Example CPU chips

• The main features of the core of an UltraSPARC
  III system

88
Example CPU chips

• The Intel 8051
• Designed for embedded system use
• 16 address lines for up to 64 K of memory
• 8-bit data bus
• Four 8-bit data ports for I/O with devices
• Buttons, LEDs, switches, etc.
• 4 KB internal ROM

Logical pinout of the 8051
89
Example buses

• IBM PC bus
• 62 lines
• 20 address
• 8 data
• 33 control
• Designed for use with Intel 8088 chip
• Control lines involved 8088 plus 6 other major
  chips

90
Example buses

• ISA bus
• Industry Standard Architecture
• 98 lines including
• 16 data lines
• Old PC boards plug into the first 62 lines
• Originally for use with the IBM PC/AT
• 8.33 MHz clock
• 2 bus cycles needed for 32-bit transfer

91
Example buses
The PC/AT bus has two components, the original PC
part and the new part
92
Example buses

• EISA bus
• Extended ISA bus
• 32 data lines
• Used with 386 / 486 / Pentium chips
• Still compatible with old PC and AT cards
• 33.3 MB / sec bandwidth
• Text calculates 135 MB / sec bandwidth needed for
  full-screed video

93
Example buses

• PCI bus
• Peripheral Component Interconnect
• Originally in 1990 . . .
• 33 MHz / 32 bit / 133 MB per second / 120 pins /
  5 volts
• More recent PCI 2.2
• 66 MHz / 64 bit / 512 MB per second / 184 pins /
  3.3 volts
• Synchronous bus
• Data and address lines are multiplexed

94
Architecture of an early Pentium system. The
thicker buses have more bandwidth than the
thinner ones
95
The bus structure of a modern Pentium 4 (bridge
chip now central)
96
Example buses

• New bus PCI Express

97
Example buses

• USB bus
• Universal Serial Bus
• Goals on page 218 of text
• Very successful
• Used for low-speed devices
• Mouse, keyboard, printer, scanner, phone, etc.
• 1.5 MB / second bandwidth
• Root hub . . .
• Plugs into main bus
• Has sockets for I/O devices or expansion hubs
• 4-wire cable
• 2 data
• Power
• Ground
• Current version is USB 2.0

98
PIO chip

• Parallel I/O
• Common chip used for I/O
• Each port is connected to an internal 8-bit
  register
• View as a 4-byte memory
• Used to implement memory-mapped I/O
• Example Writing ASCII byte to port A might cause
  the byte to be printed as a side effect

The 4th address is an internal 8-bit status
register
An 8255A PIO chip
99
Putting it all together

• Design a simple computer with . . .
• 16-bit addresses
• Maximum memory of 64K cells possible
• 16-bit Z80 CPU
• EPROM chip 2K x 8-bit
• RAM chip 2K x 8-bit
• PIO chip for memory mapped I/O

100
Address decoding

• Address format of EPROM bytes
• 00000XXXXXXXXXXX
• Address format of RAM bytes
• 10000XXXXXXXXXXX
• Address format of PIO bytes
• 11111111111111XX

All other addresses are illegal
Location of the EPROM, RAM, and PIO in our 64 KB
address space
101
Notes The high-order 2 bits select the chip The
low-order bits of each address are connected to
address pins of the EPROM, the RAM, and the
PIO Partial address decoding is used in the
complete system
102
A complete microcomputer system
Note This diagram is not in the text
103
Design with a 64K RAM memory

• Use eight 8K x 8-bit RAM chips
• Ignore the PIO
• Use the high-order 3 bits to select the RAM chip
• An 8-way decoder asserts the CS control line of
  the appropriate RAM chip
• Use the low-order 13 bits to select the address
  within the chip

C C C X X X X X X X X X X X X X
chip select address within chip