Chapter 7. Testing of a digital circuit

1
Chapter 7.Testing of a digital circuit
2
Failure any departure of a system or module from
its specified correct operation. A failure
is a malfunction. Fault a condition existing in
a hardware or software module that may lead to
the failure of the module Hardware fault
external disturbances, manufacturing
defects. Software fault design
mistake. Error an incorrect response from a
hardware or software module. An error is the
manifestation of a fault. The occurrence of an
error indicates that a fault is present in the
module. Testing fault detection/ fault location.
3
(No Transcript)
4
(No Transcript)
5
(No Transcript)
6
(No Transcript)
7
(No Transcript)
8
(No Transcript)
9
(No Transcript)
10
(No Transcript)
11
Consider the process of generating a test for
line 5/0 in fig 1.4.8. We start with the
following cube, which includes the primitive
D-cube of failure for this fault
The next step is to propagate this D farther
toward line 11. Referring to propagation D-cubes
in table 1.4.1, cube j shows that the D in cube k
is automatically propagated to lines 6 and 7.
Consider now the propagation along the path 6, 9,
11. Table 1.4.1 again shows that the D on line 6
can be moved to line 9 by using cube d. In other
words, a new cube can be obtained by combining
cubes d and k. This process of combination is
referred to as D-cube intersection.
Lines 7 and 9 now contain the change, which can
be propagated further into line 11.
12
The next step is determine a value for the
primary input line 4 since that is the only line
that has not been assigned a value. To create a
0 in line 10, both lines 7 and 8 must be a 1
however, in cube m, line 7 is a D, indicating
that cube m cannot result in a test vector along
5, 6, 9, 11. Start again from cube k to
propagate along the path 5, 7, 10, 11. This
leads to the following cube
The values of 1 and 4 are required to complete
the operation. The resulting cube are completing
lines 1 and 4 is
13
(No Transcript)
14
(No Transcript)
15
Detection of Faults in PLA

• PLA characteristic
• 1. In a circuit structure, PLA essentially has
  only two levels of gates.
• 2. A more general fault model is necessary
  because of the way PLA is fabricated.
• Fault Model incorrect logical connections in the
  AND and OR plane
• Growth (G) fault a connection in the AND plane
  is missing -gt causing the implicant to grow
• Disappearance (D) fault a connection in the OR
  plane is missing -gt causing the implicant to
  disappear
• Shrinkage (S) fault an intended connection in
  the AND plane is made -gt causing the implicant to
  shrink
• Apperance (A) fault an intended connection in
  the OR plane is made -gt causing the implicant to
  appear
• Single fault assumption Important calsses of
  multiple faults are detected by any single fault
  test set.

16

• Growth fault L (CCij ?x, D)
• Shrinkage fault L (C Cij ? a, D), a0,1
• Disappearnce fault L (C, DDij ?0)
• Appearance fault L (C, DDij ?1)
• S1 S2 S1NOT(S2)
• the cube in S1 not in S2

17

• Classification of fault-tolerant technique
• Fault avoidance
• - Environmental (dust free)
• - High quality components
• - Quality control
• 2. Fault detection make sure the system is
  working or not - Duplication
• - Error detection code parity bit -
  Self-checking - Watchdog processor

18
3. Fault masking -
Voting (triple modular redundancy) TMR NMR
- Error correcting code 4. Dynamic
redundancy reconfiguration
If one of DRAM is fault, ? DRAM fault Using
reconfiguration
Remove
Reconfiguration
Add
19
(No Transcript)
20
(No Transcript)
21
(No Transcript)
22
(No Transcript)
23
Sequential Logic Memory Problems Generating a
Test Sequence ? Initial state is unknown
controllability is required to set initial
state. ? Fault signal must be propagated to
primary outputs. Observability of final state is
required to check faulty state. Scan Design
All flip-flops in a circuit are interconnected
into one or more shift registers and the content
of the register is shifted in and out. ? Very
few additional external connections used to
access many internal nodes at the cost of
additional internal logic. ? All states
completely observed and controlled form primary
I/O.
24

• Testing Procedure in scan-path design LSSP
• Scan in test vector Yj using Xn and TCK
• Apply corresponding test vector on Xi inputs
• After sufficient time for signals to propagate,
  check output Z.
• Apply one clock pulse to SCK to enter new values
  of Yj into corresponding FFs.
• Scan out with TCK and check Yj values.
• Level-Sensitive Level stays for a certain
  period.
• Edge-Sensitive Level only at pulse change.