An 8GHz ContinuousTime SD ADC

1
An 8-GHz Continuous-Time S-D ADC in an InP-based
DHBT Technology
Sundararajan Krishnan, Dennis Scott, Miguel
Urteaga, Zachary Griffith, Yun Wei, Mattias
Dahlstrom, Navin Parthasarathy, Mark Rodwell
University of California, Santa Barbara
Now with Texas Instruments, India email
s-krishnan2_at_ti.com
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S-D ADC Introduction
 
 
High resolution using over-sampling and
noise-shaping Negative feedback used to shape
spectral char. of quantization noise Order of
linear system is order of ADC
Design can be in discrete-time(DT) or
continuous-time(CT) InP-based HBTs have shown
high cutoff-frequencies hence, high clock-rates
possible No good switches, though. Hence, design
is CT
 
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InP/InGaAs/InP Mesa DHBTTechnology Discussion -
Device Results
 
 
C
E
B

• narrow 1.7 mm base mesa, 0.7 mm emitter
• Jkirk 2e5 A/cm2 _at_ Vce 0.7 V

ft 200 GHz fmax205 GHz b 35 BVCEO 6 V
 
4
IC wiring environment
Interconnect cross-section
top view after plating ground-plane
ground plane
BCB
resistors
metal1
SiN
metal2

• Thin-film-dielectric (5 mm BCB) micro-strip
  wiring
• Reduced ground via inductance, Minimal line -
  line coupling
• 8 mm line gives controlled 50 W impedance

5
S-D ADC Introduction
 
 
Filter is second-order gm-C. Zero realized with a
series R M-S-S latch is the 1-bit quantizer.
DAC is RTZ, and is realized as a
current-steering switch
1-bit quantizer
Additional stage of regeneration used in the
quantizer to reduce meta-stability errors DAC is
RTZ to minimize SNR-degradation due to excess
delay from the additional stage of regeneration
 
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Divider test structure for the Latch
fclk 87 GHz
Latch configured as a static frequency divider
shows maximum fclk of 87 GHz Power consumed in
divider is 700mW Even at such high switching
speeds, meta-stability is a serious concern
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Effect of M-S-S latch on SNR

• Additional stage of regeneration necessary to
  minimise metastability errors
• Excess delay introduced by the additional stage
  alters quantizer input, output spectrum and
  degrades SNR
• Loss in SNR fully recovered by moving centroid
  of DAC to original position

addl. stage of regeneration
CLK
t
V
S
M-S
Idac M-S latch
S
t
Idac M-S-S latch
t
DAC
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RTZ DAC A way to recover SNR

• RTZ DAC pushes centroid forward by Tclk/4
• Zeroes of the loop can be adjusted to compensate
  for the rest of the delay (Tclk/4)

CLK
t
Idac M-S latch
t
Idac Ideal location RTZ DAC
t
t
Idac M-S-S latch RTZ DAC
t
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Final designs (10 GHz clock)
NRZ DAC
RTZ DAC
Integrator-1
Slave
DAC
Master
Slave
Integrator-2
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Analog measurements Spectrum Analyzer
10 GHz clock-rate
RTZ-DAC-based ADC has higher resolution (as
expected) Noise-floor of RTZ-DAC-based ADC evens
out at low frequencies ( lt 125 MHz) digital
acquisition needed to measure dynamic range (DR)
at lower end of spectrum accurately Both ADCs
consume 1.5W of power (mostly in the latch)
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Measurement by Digital Acquistion
In software
Logic Analyzer cannot read 8 Gbps demux to 500
Mbps Signal reconstructed in software FFT
performed in Math no dynamic-range problems
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One-tone measurements
Clock-rate 8 GHz FFT bin size 61 kHz
fin 62.5 MHz Pin 3 dBm
fin 250 MHz Pin 3 dBm

• Output power referenced to power in fundamental
  for a square-wave at that frequency
• Performance not ideal for over sampling ratios
  gt32
• Meta-stability and latch latency dominate at
  lower end of spectrum

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SNR and of bits of resolution
For an equivalent Nyquist-rate ADC, SNR and
effective of bits of resolution, ENOB, are
related by
ENOB (SNR-1.76)/6.02
Noise power measured at upper band edge
Noise power integrated to signal frequency
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Effect of latch latency on output spectrum
Spurious glitches if clock not delayed

• Clock signal to RTZ-DAC delayed (relative to
  comparator) to avoid glitches in DAC pulse
• If delay not optimum (probably the case), output
  spectrum not ideal

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Effect of comparator speed on noise-shaping

• Comparator speed increased by increasing bias
  current
• With a slower comparator, output spectrum is
  dominated by metastability at frequencies lt 150
  MHz
• M-S latches 101 faster than clock rate for low
  metastability

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Two-tone measurements
FFT bin size 61 kHz
Slower comparator lower bias
Faster comparator higher bias

• Integrator bias current gtgt RTZ-DAC current to
  achieve linearity in the input stage
• gt 80 dBc suppression of intermodulation at lower
  bias
• Same voltage source for integrator, DAC and
  comparator DAC current increases much faster
  than Integrator bias current Intermodulation
  suppression degrades with increasing bias

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Conclusions

• Demonstrated a 2nd order, continuous-time S-D
  ADC clocked at 8 GHz in a 200GHz ft, fmax
  InP-based technology
• ADC measured using both Analog and Digital
  acquisition techniques
• ADC has 48dB SNR at an OSR of 32. (Ideal
  performance is 3dB higher)
• ADC performance limited by meta-stability errors
  and latch latency at the lower end of the
  spectrum
• gt 75dBc suppression of intermodulation-products
  observed