ECE 747 Digital Signal Processing Architecture SoC Lecture

1
ECE 747 Digital Signal Processing
ArchitectureSoC Lecture SoC Simulation
Strategy
March 27, 2007 W. Rhett Davis NC State
University
2
Todays Lecture

• Why to use SoC Designer
• FIR_cascade_DF example in SoC Designer

3
Our Goal
Determine the quality of our Accelerator
Componentin terms of

• Area (cost)
• Clock Frequency (constraint on system clock
  freq.)
• Power (battery life/MTTF)
• Throughput
• Latency

Knowing these things allow us to determine if
there is a market for our design
4
How will you find the following?

• Area
• Clock Frequency
• Power
• Throughput
• Latency

5
ARM1176JZF Characteristics

• In a 90nm process, at 1V, optimized for speed
• Area 2.65 mm2
• Clock Frequency 620 MHz
• Power 0.45 mW/MHz (source www.arm.com)
• Well need to scale these numbers to be
  compatible with our Design Compiler results

6
Theoretical vs. Observed Throughput

• Our accelerators will have a theoretical maximum
  throughput when simulated by themselves
• When simulating with a complete system, the
  memory accesses become a bottleneck, leading to a
  smaller observed throughput
• observed average throughput (results per cycle)
  total no. of results / total no. of cycles
• We need the realistic model of the interconnect
  and memory in SoC Designer to accurately
  characterize the observed throughput

7
Todays Lecture

• Why to use SoC Designer
• FIR_cascade_DF example in SoC Designer

8
Similarity to SystemC Flow

• Like the SystemC Simulation Flow, this flow will
• Use the files Data.txt for input values and
  Coeffs.txt to configure the filter
• Output to the file Output.txt with filtered
  values
• Use a standard SystemC module communicating
  through sc_signal and sc_fifo channels.
• Unlike the SystemC flow
• Test-bench will be discarded
• Module needs a reset method

9
System Overview
10
Simulation Timeline