Subtraction, Multiplication, Sequential Circuits

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Subtraction, Multiplication,Sequential Circuits

• Anselmo Lastra

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Administrative

• Test next Thursday, 2/6
• Or the following Tuesday (2/11)?

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Topics

• More Verilog
• To prepare for lab
• 1s and 2s complement
• Adder-Subtrator
• Signed addition, subtraction
• Multiplication
• Sequential Circuits
• Latches

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More Verilog

• Constructs that youll use in lab
• Especially for testing
• Testing by creating waveforms with graphical tool
  too tedious
• Write program to create test vectors

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Initial

• Statements run when program begins
• initial
• begin
• statements
• end

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Blocking Assignment

• Equal sign indicates blocking statements
• initial
• begin
• B A
• C B
• end
• Result is that new contents of B are in C, so all
  have contents of A.

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Non-Blocking Assignment

• lt indicates non-blocking statements
• initial
• begin
• B lt A
• C lt B
• end
• All RHS evaluated first, then assigned
• Result is that old contents of B are in C
• Wont need for testing

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Delay

• The sign and an integer indicates a delay
• initial
• begin
• A 4'd0 B 4'd0 C0 1'b0
• 50 A 4'd3 B 4'd4
• end
• You can indicate time scale at top of testbench
  file (units and time step)
• timescale 1ns/1ns

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Simple Testbench (Friday lab)

• initial
• begin
• A 4'd0 B 4'd0 C0 1'b0
• 50 A 4'd3 B 4'd4
• 50 A 4'd2 B 4'd5
• 50 A 4'd9 B 4'd9
• 50 A 4'd10 B 4'd15
• 50 A 4'd10 B 4'd5 C0 1'b1
• 50 A 4'd0 B 4'd0 C0 1'b0
• 50 A 4'b1111 B 4'b1111 C0 1'b1
• end

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Simple Loop

• Can use for statement in an initial block
• integer k
• for(j 0 j lt 4 j j 1)
• begin
• 50 A A 1
• end

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Printing

• initial
• begin
• monitor(time,
• "Ab,Bb, c_inb, c_outb, sum b\n",
• A,B,C0,C4,S)
• end
• The monitor directive prints whenever any of the
  variables changes
• display just prints useful for headers
• See Verilog references

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Experiment

• Suggest you spend some time experimenting
• Write some programs to test your designs
  different ways

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Back to addition

• Had looked at signed arithmetic
• Subtraction caused problems
• Had to selectively compute twos complement in
  separate circuit
• Review 1s and 2s complement
• See how that will make circuits simpler

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1s Complement

• Given binary number N with n digits
• 1s complement defined as
• (2n 1) - N
• Note that (2n 1) is number with n digits, all
  of them 1
• For n 4, (2n 1) 1111

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Example

• Notice that 1s complement is complement of each
  bit

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2s Complement

• Given binary number N with n digits
• 2s complement defined as
• 2n N for N ? 0
• 0 for N 0
• Exception is so result will always have n bits
• 2s complement is just a 1 added to 1s complement

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Property

• Complement of a complement generates original
  number
• NOTE We havent talked about negative numbers
  yet. Still looking at unsigned
• Lets look at new design for subtractor

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New Algorithm for M-N

• Add 2s complement of N to M
• This is M (2n N) M N 2n
• If M ? N, will generate carry (why?)
• Discard carry
• Result is positive M - N
• If M lt N, no end carry (why?)
• Take 2s complement of result
• Place minus sign in front

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Example

• X 101_0100 minus Y 100_0011

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Example 2

• Y 100_0011 minus X 101_0100
• No end carry
• Answer - (2s complement of Sum)
• - 0010001

We said numbers are unsigned. What does this
mean?
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Adder-Subtractor

• Need only adder and complementer for input to
  subtract
• Need selective complementer to make negative
  output back from 2s complement
• Or go through adder again. See next slide

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Design
S low for add, high for subtract
Inverts each bit of B if S is 1
Adds 1 to make 2s complement

• Output is 2s complement if B gt A

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Signed Binary

• First review signed representations
• Signed magnitude
• Left bit is sign, 0 positive, 1 negative
• Other bits are number
• 2s complement
• 1s complement

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Example in 8-bit byte

• Represent -9 in different ways
• Signed magnitude 10001001
• 1s Complement 11110110
• 2s Complement 11110111

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Observations

• 1s C and Signed Mag have two zeros
• 2s C has more negative than positive
• All negative numbers have 1 in high-order

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Advantages/Disadvantages

• Signed magnitude has problem that we need to
  correct after subtraction
• Ones complement has a positive and negative zero
• Twos complement is most popular
• Arithmetic operations easy

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Twos Complement

• Addition easy on any combination of positive and
  negative numbers
• To subtract
• Take 2s complement of subtrahend
• Add
• This performs A ( -B), same as A B

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Examples from Book

• Addition
• 6 13
• -6 13
• 6 - 13
• -6 -13
• Subtraction
• -6 - (-13)
• 6 13
• Try some of these

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Overflow

• Two cases of overflow for addition of signed
  numbers
• Two large positive numbers overflow into sign bit
• Not enough room for result
• Two large negative numbers added
• Same not enough bits
• Carry out can be OK

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Examples

• 4-bit signed numbers
• 7 7
• 7 7
• Generates carry but result OK
• -7 -7

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Overflow Detection

• Condition is that either Cn-1 or Cn is high, but
  not both

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Multiplier

• Looked at this in first week
• Multiply by doing single-bit multiplies and
  shifts
• Look at combinational circuit to do this

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Combinational Multiplier
AND computes A0 B0
Half adder computes sum. Will need FA for larger
multiplier.
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Larger Multiplier
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Later Sequential Multiply

• Imagine doing over time rather than in parallel
• Bitwise multiply
• Shift
• Add

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Sequential Circuits

• To do that, we need to store data
• State of system is info stored
• That, and inputs, determine outputs

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Types of Sequential Circuits

• Synchronous
• State changes synchronized by one or more clocks
• Asynchronous
• Changes occur independently

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Clocking of Synchronous

• Changes enabled by clock

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Comparison

• Synchronous
• Easier to analyze because can factor out gate
  delays
• Set clock so changes allowed to occur before next
  clock pulse
• Asynchronous
• Potentially faster
• Harder to analyze
• Will look mostly at synchronous

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Basic Storage

• Apply low or high for longer than tpd
• Feedback will hold value

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SR (set-reset) Latches

• Basic storage made from gates

• S R both 0 in resting state
• Have to keep both from 1 at same time

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Operation
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Latch

• Similar made from NANDs

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Add Control Input

• Gates when state can change

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D-type Latch

• No illegal state

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Topics

• Today
• Wrapped up combinational design
• Looked at basic latches
• Next Time
• Flip-flops
• Verilog for sequential circuits