Random Number Generator

1
Random Number Generator

• Dimtriy Solmonov W1-1
• David Levitt W1-2
• Jesse Guss W1-3
• Sirisha Pillalamarri W1-4
• Matt Russo W1-5
• Design Manager- Thiago Hersan

2
Status

• Finished
• C implementation
• Architecture
• Verilog Datapath design
• In Process
• Simulation
• Gate-Level Design
• Preliminary Floorplan
• Unfinished
• Schematic
• Layout
• Extraction, LVS, post-layout simulation

3
Design Decisions

• Alpha 8
• 2 sets of 32 x 32 SRAM
• One dual bus SRAM
• Main adder unit chosen

4
Pipeline Version 5.1

• 2 Stages
• 5 clock cycles (ticks) per stage.
• Not all registers update on the same tick value
• Assumptions
• 32-bit addition in two ticks
• SRAM read in half a tick

5
Random Numbers

• With original seed of all 1s
• AA38AF8A8F2361738A122CBF4511461C16055A026C1021764F
  D9254F66608094E6713B5D9A144E7F7385D61A5B443B0824C6
  B5AE5BB18535C0A09FE6329950D1DDA642BB07632F26A872E0
  48E203327C1F55BC126A8A2B814D5F1E23CB71565F89573017
  60242573DAF0A1E41C9E89DC7DCEF91FE25B7F55B1419A4912
  9EF5
• 81B1CC28F282CD1C80749611EADE85E278B3DE0519C6594354
  18F4C24399F7014A1505974E2AF4974C45AC92BEDC8D3B07FB
  4E7F60D81C86C0715742A600BE0152B4E6D4DF2A93B5075B5B
  1AA8CF406F5EAE2589287D9DAF745C105989132A98A8580280
  26431FFE94E5C224890BCA1E3CF28F6C56A247C2912A8BBCD7
  9AF

6
Project Main Blocks
7
Main DataPath
8
Stage 1
Receive I, I_prev. -------------------------------
----------------------------------- 0) M1Mi32
A1(Altlt19) (Agtgt13) ---------------------------
--------------------------------------- 1)
XMi AA1M1 ---------------------------------
--------------------------------- NOTE Y get's
updated at start of this tick 2) M3MX
AA1M1 C1(Xi-1) ---------------------------
--------------------------------------- 3) Y1A
(C1) ? Y M3 ------------------------------------
------------------------------ 4) Y1 A
M3 -----------------------------------------------
-------------------
9
Stage 1
10
Stage 2

• Receive B, Y1, X, I.
• --------------------------------------------------
  --------------------
• 0) YBY1 YLB130Y1130
• --------------------------------------------------
  --------------------
• 1) YBY1 M4MY138 C2(IY138)
• --------------------------------------------------
  --------------------
• 2) B X(C2) ? Y M4
• --------------------------------------------------
  --------------------
• 3) B X(C2) ? Y M4 MiY
• --------------------------------------------------
  --------------------
• 4) Ri B
• --------------------------------------------------
  --------------------

11
Stage 2
12
Other optimizations

• Memory and registers updated at different edges
  of clock.
• One special adder