Random Number Generator

1
Random Number Generator

• Dimtriy Solmonov W1-1
• David Levitt W1-2
• Jesse Guss W1-3
• Sirisha Pillalamarri W1-4
• Matt Russo W1-5
• Design Manager Thiago Hersan

2
A Quick Review

• Applications encryption, gambling, personal
  computers, etc.
• Goal faster random number generation than
  current software.
• Algorithm
• 1028 bit seed fed into RAM
• Feedback loop repeats 256 times to hash the seed
  and produce a pseudorandom number.
• Two stage, five clocks per stage pipeline.

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Status

• Last Time
• C implementation
• Architecture
• Behavioral Verilog Datapath design
• This Week
• Finished Simulation
• Gate-Level Design
• Preliminary Floorplan
• In Process
• Schematic
• Unfinished
• Layout
• Extraction, LVS, post-layout simulation

4
Design Decisions

• Finalized interface between chip and outside
  world.
• Sense amps on SRAM

5
Chip Interface
Design Decisions 2

• 64 IO pins for seed, random number.
• Other inputs
• Reset
• Generate
• Read
• Clock
• Other outputs
• Ready
• Done

6
Sense Amps
Design Decisions 3

• Problem with bus charge time.
• Amplifiers that detect small changes in voltage
  and quickly ramp them up to high voltage.

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32 Bit Adder

• Three adders execute 256 times each to generate
  one number.
• Hybrid carry skip, carry look ahead, carry
  select
• Fast and low power.
• Chirca, Schulte, Glossner, et al. A Static
  Low-Power, High-Performance 32-bit Carry Skip
  Adder
• http//mesa.ece.wisc.edu/publications/cp_2004-12.p
  df

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Block Diagram
32-Bit Adder 2
A2710
B2710
A3128
B3128
A30
B30
A94
B94
C0
C4
C10
C28
C32
CS4
CS18
CS6
CS4
S3128
S2710
S94
S30
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First CS4 Block
32-Bit Adder 3
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CS6 Block
32-Bit Adder 4
12
CS18 Block
32-Bit Adder 5
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Second CS4 Block
32-Bit Adder 6
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Other Progress

• Synthesis of gate level Verilog from behavioral
  FSM and other control logic.
• Updated transistor count.
• Further developed floor plan and rough sizes.

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Transistor Count
Block Name Original Estimate Transistor Count (Alpha 6) Current Transistor Count (Alpha 8)
SRAM 6,000 15000
Fast Hybrid Adder x3 4,000 7200
FSM and Datapath 4,000 FSM 230 Datapath 9600
Total 14,000 27,030
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Floor Plan
725 um²