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ECE6130: Computer Architecture: Instruction Set Architecture

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Title: ECE6130: Computer Architecture: Instruction Set Architecture


1
ECE6130 Computer ArchitectureInstruction Set
Architecture
  • Dr. Xubin He
  • http//www.ece.tntech.edu/hexb
  • Email hexb_at_tntech.edu
  • Tel 931-3723462, Brown Hall 319

2
  • Previous Class
  • Introduction ot ISA
  • ISA classification
  • Today
  • Memory addressing

3
Memory Addressing
  • Addressing Memory how to specify and interpret
    memory address is important since all data are
    initially in the memory.
  • Interpreting Memory Addresses
  • All computers, except DSPs, are byte-addressed,
    providing access for bytes, half-words (2 bytes),
    words (4 bytes), and double words (8 bytes)

4
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5
Memory Addressing
  • Ordering bytes within a larger object 8 bytes in
    a double word
  • Little Endian
  • Big Endian

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8
Memory Addressing
  • Alignment of bytes
  • an access to an object of size s bytes at byte
    address A is aligned if A mod s 0.
  • Memory is aligned on a multiple of a word or
    double-word boundary
  • In general
  • object larger than 1 byte must be aligned to
    reduce HW complexity

9
Text Book, Figure 2.5
10
Addressing Mode
  • How architectures specify an address of an object
    to be accessed
  • Addressing mode can specify
  • Constant
  • Register
  • Location in memory (effective address)
  • See figure 2.6
  • PC-relative addressing a displacement mode using
    PC as register and used primarily for specifying
    code addresses in branches
  • Complex addressing mode
  • Reduce instruction counts a lot
  • Add complexity (may increase the cycle time)
  • Increase average CPI
  • Know what modes to include is important

11
Figure 2.6 addressing modes (page 98)
12
What Addressing Modes are Common?
  • Measure VAX using three SPEC89, which supports
    all Addressing modes in figure 2.6
  • Immediate and displacement dominate (not
    including PC-relative and register)
  • See figure 2.7

13
Figure 2.7 summary of memory addressing mode
14
Immediate or Literal AM
  • Use of immediate
  • Arithmetic operations
  • Comparisons (primarily for branches)
  • Moves where a constant is wanted in a register
  • Constants written in code (small)
  • Add reg , 2
  • Address constants (large)
  • Need to know whether they need to be supported by
    all Ops or for only a subset

15
Frequency of Immediate for Different Instructions
  • Very high in ALU and comparisons gt many are 0
  • See figure 2.9
  • Data taken on Alpha architecture with full
    optimization for SPEC CPU 2000, integet CINT2000
    and FP CFP2000

16
Figure 2.9 CINT2000 in SPEC CPU 2000
17
Range of Immediate Values
  • Range affects instruction length
  • Small values are most common
  • Large values sometimes address calculations
  • See figure 2.10
  • Data taken on Alpha architecture with full
    optimization for SPEC CPU 2000, integet CINT2000
    and FP CFP2000

18
Figure 2.10 distributions of immediate values
19
Displacement Addressing Mode
  • What ranges Displacement used?
  • Various displacement sizes determine the length
    of the displacement field -gt length of
    instructions
  • Displacement for data accesses (not branches)
  • See figure 2.8

20
Figure 2.8 displacement values
21
Memory Addressing Summary
  • Use a GPR machine a reg-reg one
  • A new ISA at least support the following
    addressing modes
  • Displacement
  • Immediate 75-99 of AM
  • Reg indirect
  • Size of the address for displacement modes to be
    at least 12-16 bits gt 75-99 of displacements
  • Immediate field is at least 8-16 bits gt
    capture 50-80 of immediates

22
Next
  • Type and size of operands
  • Operations
  • Read Chapter 2.5-2.8
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