Figure 10.1 CISSC versus RISC instruction execution

1
Figure 10.1 CISSC versus RISC instruction
execution
2
Figure 10.3 Power PC integer arithmetic
instruction format
3
Figure 10.5 Circular register buffer (a)
current window, (b) after window shift
4
Figure 10.5 (continued)
5
Figure 10.6 Fetch-execute cycle for
register-to-register move instruction
6
Figure 10.7 Moving the address space to address
more memory
7
Figure 10.8 Base register address creation
8
Figure 10.9 Load instruction format
9
(No Transcript)
10
Figure 10.10 Fetch-execute cycle for relative
addressing
11
Figure 10.11 Example of LMC immediate addressing
12
Figure 10.12 Fetch-execute cycle with immediate
addressing
13
Figure 10.14 Little Man indirect addressing
14
Figure 10.14 (continued)
15
Figure 10.17 Obtaining the data with register
indirect addressing
16
Figure 10.18 68000 MOVE instruction format
17
Figure 10.19 Modifying an address with an index
register
18
Figure 10.20 Indexing a base offset address
19
Figure 10.22 Fetch-execute timing diagram
20
Figure 10.23 Pipelining
21
Figure 10.24 Alternative CPU organization
22
Figure 10.25 A more general CPU block diagram
23
Figure 10.26 Scalar versus superscalar processing
24
Figure 10.27 Modern CPU block diagram