Concurrent Test Generation

1

• Concurrent Test Generation

Vishwani D. Agrawal Alok S. Doshi
Auburn University, Department of Electrical and
Computer Engineering Auburn, AL 36849, USA
Asian Test Symposium (ATS), December 18-21, 2005
2
Problem Statement

• To find the smallest test set to detect all
  single stuck-at faults in a combinational
  circuit.
• An existing solution
• Group faults into fault sets using fault
  independence
• Generate concurrent tests for each group
• Contribution of this paper Devise a
  simulation-based implementation to this solution.

3
Outline

• Introduction
• Simulation-based Independence Fault Collapsing
• Simulation-based Concurrent Test Generation
• Results
• Conclusions

4
Introduction

• Problem of finding a minimal test-
• Static compaction cannot guarantee optimality.
• Dynamic compaction is complex.
• Solution Target both faults F1 and F2 at the
  same time to find a single test.

.
.
.
T(F2)
T(F1)
Test set for fault F2
Test set for fault F1
v2
v1
v3
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Fault Classification
T(F1)
T(F1) T(F2)
T(F2)
F1 and F2 are equivalent.
F1 dominates F2.
T(F1)
T(F2)
T(F1)
T(F2)
F1 and F2 are independent.
F1 and F2 are concurrently testable.
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Example Circuit
2
4
a
x
1
5
b
3
7
11
c
y
d
6
10
9
All faults are Stuck-at-1 type
e
8
C17 - ISCAS85 Benchmark Circuit
1 R. K. K. R. Sandireddy and V. D. Agrawal,
Diagnostic and Detection Fault Collapsing for
Multiple Output Circuits, Proc. Design,
Automation and Test in Europe (DATE) Conf., Mar.
2005, pp. 1014 - 1019.
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Independence Matrix and Graph
F 1 2 3 4 5 6 7 8 9 10 11
1 0 1 1 1 1 1 0 0 1 0 1
2 1 0 0 1 1 0 1 0 0 0 1
3 1 0 0 0 1 1 1 1 0 1 1
4 1 1 0 0 1 0 1 0 0 0 1
5 1 1 1 1 0 0 0 1 1 1 0
6 1 0 1 0 0 0 1 1 1 0 0
7 0 1 1 1 0 1 0 1 1 0 0
8 0 0 1 0 1 1 1 0 1 1 1
9 1 0 0 0 1 1 1 1 0 1 1
10 0 0 1 0 1 0 0 1 1 0 1
11 1 1 1 1 0 0 0 1 1 1 0
C17 - ISCAS85 Benchmark Circuit
8
Independence Fault Collapsing
A similarity based algorithm 2 collapses the
independence graph
5,11,7
1,8
3,9,2
4,6,10
C17 - ISCAS85 Benchmark Circuit
2 A. S. Doshi and V. D. Agrawal, Independence
Fault Collapsing, Proc. 9th VLSI Design and Test
Symp., Aug. 2005, pp. 357 - 364.
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Simulation-based Independence Fault Collapsing

• The independence graph generation procedure 2
  requires ATPG.
• Here we present a new method for graph generation
  using simulation
• Start with a fully-connected independence graph
  for an equivalence collapsed fault set.
• Simulation of random vectors without fault
  dropping removes edges between faults detected by
  the same vector.

2 A. S. Doshi and V. D. Agrawal, Independence
Fault Collapsing, Proc. 9th VLSI Design and Test
Symp., Aug. 2005, pp. 357 - 364.
10
Simulation-based Independence Fault Collapsing
301
74181 4-bit ALU
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Simulation-based Concurrent Test Generation

• For each group, generate all test vectors for the
  first fault in the group.
• If the number of test vectors for a fault is
  large, use a subset (e.g., 250 maximum) of
  vectors.
• Simulate all faults in the group to select one
  vector that detects most faults in that group.
• If more vectors than one detect the same number
  of faults within the group, then select the
  vector that detects most faults outside the group
  as well.

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74181 4-bit ALU Result
Group Number Number of faults in group Concurrent Test Vector
1 2 3 4 5 6 7 8 9 10 11 12 13 9 15 11 6 11 17 11 16 16 22 22 56 81 01100011111100 01101100000110 10100101111010 11011010100000 10110101011010 10100111101010 10010101001110 01000111101011 11100010010011 11011100110100 01010001100001 No test needed. 10101001110110
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Results
Circuit No. of concurrent groups Concurrent ATPG Concurrent ATPG Single-fault ATPG Single-fault ATPG Single-fault ATPG Single-fault ATPG
Circuit No. of concurrent groups Vectors CPU s Atalanta Atalanta Best known Best known
Circuit No. of concurrent groups Vectors CPU s Vectors CPU s Vectors CPU s
1-b adder 2-b adder 4-b adder 8-b adder 16-b adder 32-b adder 4-b ALU c17 c423 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 5 5 5 7 7 7 13 4 30 52 24 84 106 81 107 92 23 190 5 5 5 7 9 11 12 4 34 52 29 84 111 92 130 104 25 198 0.085 0.092 0.103 0.182 3.3 9.7 11.4 0.082 10.4 14.6 23.3 34 49.6 57.6 119.6 216.3 158.1 360.7 5-7 7-9 8-11 10-15 13-22 17-25 22-40 6-9 49-77 54-68 52-106 85-109 118-173 106-192 147-263 114-224 32-48 209-358 0 0 0 0 0.017 0.050 0.033 0 0.083 0.033 0.133 0.1 0.5 1.2 1.9 0.733 4.7 5.283 5 5 5 5 5 5 12 4 27 52 16 84 106 44 84 37 12 73 - - - - - - - - 15 0.1 21.9 0.9 88.1 47.1 174.5 748.6 347.7 663.8
Sun Ultra 5 Pentium Pro PC
Hamzaoglu and Patel, IEEE-TCAD, 2000
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Conclusions

• Concurrent test generation produces compact tests
  when combined with independence fault collapsing.
• ATPG and set covering problems have exponential
  time complexities. Hence, we cannot expect
  absolute optimality for large circuits.
• The concurrent ATPG procedure of this paper gives
  significantly smaller, and sometimes the optimum,
  test sets.

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• Thank You!