Thermal Via Planning for 3D ICs

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Thermal Via Planning for 3-D ICs

• Jason Cong, Yan Zhang
• VLSI CAD Lab
• Computer Science Department
• University of California, Los Angeles
• Supported by DARPA and CFDRC

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Outline

• 3-D IC Technology and the Thermal Challenge
• Related Works on Thermal TS Via Planning
• An NLP Thermal TS-Via Planning Problem
  Formulation
• Multilevel Alternating Direction Via Planning
  Method
• Experimental Results and Conclusions

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3-D IC Technology Alternatives
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Thermal Challenges in 3-D ICs

• Key Challenge of 3-D IC Design
• Higher power density due to the higher device
  density
• Inter-layer dielectric layers are poor thermal
  conductors
• High Temperature Effects
• Longer interconnect delays
• Functional failure

Temperature increases dramatically along the Z
direction
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3-D IC Cooling Schemes

• Heat Sink Optimization
• Air cooling fans
• Heat radiating fins
• Not enough for 3-D ICs
• Chip-Level Temperature Optimization
• Microchannel cooling
• Temperature optimization during floorplanning and
  placement
• Temperature aware routing
• Thermal via insertion

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Through-the-Silicon Vias (TS-Vias)

• Effective in heat dissipating
• Two types of TS-vias
• Signal TS-vias, part of the netlist
• Thermal TS-vias, with no connections, introduced
  to reduce temperature

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Thermal TS-Via Planning

• Motivation
• TS vias are expensive to make and are large in
  size
• Take additional chip area and routing resource
• Previous work
• TS via planning during and after routing Cong
  and Zhang, ASPDAC05
• ASPDAC 05 VPPT ? Via Planning Proportional to
  Temperature
• TS via planning during placement Goplen and
  Sapatnekar, ISPD05
• Our approach
• TS-Via planning during routing
• Extend the TS-Via planning framework in ASPDAC05
• Multilevel alternating direction via planning
  (m-ADVP)

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Thermal Model Assumptions
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Thermal Resistive Network ITherm 2004

• Device layer partitioned into tiles
• Tiles connected through thermal resistances
• Heat sources modeled as current sources
• Heat sinks of fixed temperature T0
• TS vias at the center of the tile

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Multilevel TS-Via Planning and Routing Framework
(1). Power Density Calculation (2) TS-Via
Position Estimation (3). Heat Flow
Estimation (4). Routing Resource Estimation
(1). Signal TS-Via Assignment (2). TTS Via
Planning (3). TTS Via Number Adjustment (4)
Routing Refinement
(1). Power Density Coarsening (2). Heat Flow
Estimation (3). Routing Resource Coarsening
(1). Init Routing Tree Generation (2). Thermal TS
Via Planning (3). TTS Via Number Adjustment



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Thermal TS-Via Planning Problem

• Input
• 3-D floorplanning/placement result
• 3-D Planning Grid X?Y?Z
• Temperature constraint, such as 77OC
• Signal TS-Via number and locations
• Output
• Thermal TS-via number at each grid
• Objectives
• Thermal TS-via number minimization

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Thermal TS-Via Planning ? An NLP Formulation

• Variable Definitions
• for tile i, j, k
• ai,j,k TS-via number
• Ri,j,k thermal resistance
• ? constant Ri,j,k ? / ai,j,k
• Vi,j,k temperature
• Ii,j,k heat flow

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Thermal TS-Via Planning ? An NLP Formulation

• Objective
• Constraints
• Temperature constraint
• Capacity constraint
• Kirchhoffs current law
• Constrained NLP
• Can be solved by general NLP solver
• But expensive

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Alternating Direction TS-Via Planning (ADVP)

• Decompose the NLP into simplified sub-problems
• Optimize the via distribution at one direction at
  a time
• Alternate between vertical via planning and
  horizontal via planning at each level

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Vertical TS-Via Planning

• Resistive network ? resistive chain
• NLP ? convex programming
• Solvable by any convex programming tool
• Theorem
• no capacity constraint TS-via number
  proportional to the square root of temperature
  increase
• VPPT

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Horizontal TS-Via Planning

• Still an NLP
• Further simplification
• Given TTS via number
• Even temperature distribution in one layer
• Challenges
• Huge obstacles/heat sources
• Distribution by temperature (VPPT) not sufficient

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Horizontal TS-Via Planning by Heat Flow Estimation

• Horizontal TS-Via Planning
• Starting from even TS via distribution
• TS-via number proportional to the vertical heat
  flow Ii,j,k
• Fast Heat Flow Estimation
• Through path counting
• Assume even temperature distribution at layer k-1
• Considering the M shortest paths from tilei,j,k
  to layer k-1
• Heat flow on each path inversely proportional to
  the path thermal resistances
• Can be corrected by exact model

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Experiment Setup

• Resistive network thermal model from CFDRC
• 3D Floorplanning results from Cong, et al,
  ICCAD04
• MCNC and GSRC floorplanning benchmarks
• Power density, random value (105 107 W/m2)
• Required Temperature, 77C

benchmark characteristics
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Experimental Results ? Temperature Reduction

• With thermal via insertion, temperature can be
  reduced to the required temperature (77C)
• Thermal via insertion can reduce the maximum
  on-chip temperature by over 40

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Experimental Results ? m-ADVP vs. Solving NLP

• Solving NLP can reduce TS-via number by 1 over
  m-ADVP
• m-ADVP is over 200x faster than solving NLP

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Experimental Results ? Different TS-Via Planners

• Compared to flat ADVP, multilevel ADVP can reduce
  TS via by 11
• Compared to TS-via insertion by temperature
  (m-VPPT), m-ADVP can reduce TS via by 68
• Compared to post processing of even TS via
  distribution, m-ADVP can reduce the TS-via number
  by 3.5x

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Thermal TS-Via Distribution for ami49 Bottom Layer
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Experimental Results ? Final Routing Results

• Average completion rates for m-ADVP, m-VPPT and
  even are 96.9, 93.7 and 73.44
• Compared to m-VPPT, m-ADVP can reduce routing
  time by 49, compared to even distribution ,
  m-ADVP can reduce routing time by 3.8x

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Temperature Maps of ami33 Top Layer
After Thermal Via Insertion
Before Thermal Via Insertion
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Conclusions and Future Work

• Conclusions
• NLP formulation of the TTS-via planning problem
• ADVP tries to solve NLP through solving a series
  of sub-problems
• m-ADVP is both effective and fast in reducing the
  required TS-via number
• Future Work
• Consideration of routing congestion and
  wirelength
• Application during floorplanning/placement

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THE ENDThank You!
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Thermal Basics

• Clock cycle ltlt time constant of heat conduction
• Steady State Heat Equation
• s.t. at the
  bottom
• at other
  sides
• g is the power density , k is thermal
  conductivity, T is temperature
• Mostly Used Thermal Models
• Numerical computing, FEM Chu, THERMINIC
  workshop95, FDM Wang, ISPD03Tsai, TCAD00
• Resistive network, Huang, DAC04 Wilkerson,
  MIXDES04
• Simplified closed-form method