Title: Copper Metallization Technology
1Copper Metallization Technology
- Michael .A. Awaah
- Elec 7730 Advanced Plasma Processing for
Microelectronic Fabrication - (Second Presentation)
- Instructor Dr. Y. TZENG
2Outline
- Overview/Introduction
- Questions
- Al interconnects
- Copper Interconnects
- Damascene Technology
- Metal Deposition techniques
- Conclusion
3Questions
- Why is copper metal interconnection the metal of
choice for next generation? - Why does MOCVD seem to be the technology of
choice for copper metallization ?
4Overview
- Today, the demand for faster and more reliable
chips with larger scale of integration is bigger
than ever. - Modern ICs contain tens to hundreds of millions
of logic devices to achieve, - complex functions
5Overview
- In the past thirty years, interconnects have
evolved from a single layer of Al to multiple
levels of sandwiched Ti/Al-Cu/TiN metal layers in
ILD SiO2 - For todays technology node and beyond, Aluminum
is no longer suitable - gt relatively high resistance (2.66um-Ohm)
- gt Electromigration
- Interconnects which are embedded in interlayer
dielectric material (ILD) are the wire
connections to supply electrical signals to these
devices
6Introduction
- The major reasons for introducing the copper as
the new interconnect metal into the next
generation ICs stem from the well-established
trends in the IC manufacturing - the goal is to produce ICs with larger scale of
integration, higher device density, lower power
consumption and faster clock times
7Introduction
- There is also an enormous impetus to reduce the
process complexity and cost. - these should be achieved without compromising
with the reliability. - Increased chip size
- translates into longer global interconnect wires.
- At the 100 nm technology node, which will be
introduced for volume manufacturing in the year
2005, ICs are planned to be 5 cm2 in size with 8
levels of interconnects and the total wire length
of about 5 kilometers. These chips will operate
at 2 GHz with power supply voltage of 1.2 V or
less.
8Introduction
- Achieving these ambitious goals necessitates
substantial changes in the interconnection
technology - new materials for both ILD and interconnection
should be developed to improve delay times. - interconnect delays become a higher percentage of
the total delay time at each new technology node.
9Al problems
- The main reliability problem with current Al
interconnection is - the electromigration at higher current densities.
- Electromigration (EM) is defined atomic diffusion
in an electric field created by high current
densities. - Copper lines are less prone to electromigration.
10EM Damages
- EM damage results from occurrence of
electromigration flux divergences at grain
boundary triple points. - It can significantly reduce the reliability of
the IC as it can be manifested as hillocks on
film surfaces, bridges between two conductor
lines or discontinuity.
11EM Damages
( a) Hillock formation, (b) whisker bridging
between two conductor lines, (c) mass
accumulation and depletion
http//www.mse.berkeley.edu/groups/doyle/serdar/RE
SEARCH/copper.pdf
12Motivation for copper interconnection
- Copper has several properties that make it very
attractive for interconnection - copper has a lower resistance (resistivity for
Cu 1.67, for Al 2.66 and for Al-alloys 3.5
?-cm) - RC time delay is defined as the time it takes for
the voltage to reach 63 of its initial value at
one end to a metal line when a step input is
presented at the other end of the line. - Copper has a higher melting point (1083 oC) than
aluminum (660 oC), which leads to greater EM
resistance. -
R. Frankovic and G. H. Bernstein,
Electromigration Drift and Threshold in Cu
Thin-Film Interconnects, IEEE Transactions on
Electron Devices, Vol. 43, No.12, pp. 2233-2239.
13Motivation for copper interconnection
- This lower resistance is critically important in
high performance ICs. - enables signals to move faster by decreasing the
RC time delay.
Comparison of effective resistivity versus
linewidths of trenches for copper and Al-Cu
alloyinterconnection
Steigerwald, J. M., Murarka, S. P., Gutmann, R.
J., Chemical Mechanical Planarization of
Microelectronic Materials, p.10-26, Wiley, 1997
14Motivation for copper interconnection
- Copper interconnection reduce the capacitance
- thinner copper interconnect lines
- low-k matrix
- one can build ICs which would consume
substantially lower amounts of power due to
decrease in the total RC (resistance x
capacitance).
Intrinsic gate delay and interconnect RC delay at
minimum design rules of each node
Steigerwald, J. M., Murarka, S. P., Gutmann, R.
J., Chemical Mechanical Planarization of
Microelectronic Materials, p.10-26, Wiley, 1997
15Copper Interconnection
- There are two reasons for the reduction in the
costs - tighter packing densities with copper.
- damascene architecture
- which is the new process to form the copper
interconnect lines.
One of the main benefits of copper beyond the
ability to increase chip speed and reduce power
consumption is that the number of metal levels
can potentially reduces as much as half
16Copper Interconnection
- Damascene process requires 20-30 fewer steps
than traditional subtractive patterning. - especially use of dual damascene (in which both
the via and the interconnect are formed at the
same time) - eliminates the involvement of most difficult
steps such as aluminum etch, and many tungsten
and dielectric CMP steps.
17Ways to get fine Cu lines
- Subtractive etch
- Dry etching using Chlorine Plasma
- Main problem is low rate, improved with
several - methods
- Damascene (CMP)
- Currently used, Unavailable when feature size
- down to 0.1um
- Thermally Produce the CuO, then etch it away with
an organic acid (hfacH) - High etching rate of CuO, 1um/min at 423K
- Low rate of oxidation and the
incompatibility with - plasma
-
Chlorine PlasmaCopper Reaction in a New Copper
Dry Etching Process Journal of The
Electrochemical Society, 148 9! G524-G529 2001
18Figure of Merit
Comparison of copper interconnection with low-k
ILD material versus traditional aluminum
interconnection with SiO2
Advantages of Novellus Web Page from
http//www.novellus.com/damascus/boc/boc.htm
19Damascene Technology
- Single Damascene
- The fundamental difference of damascene relative
to the standard processing is that the metal
lines are not etched, but deposited in "grooves"
within the dielectric layer, and then excess
metal is removed by chemical-mechanical
planarization (CMP). - Dual-Damascene
- The differences of dual damascene relative to
single damascene processing are that the plugs
are filled at the same time as the metal lines.
Several processing options exist for
dual-damascene, the currently preferred method,
since the thickness of the metal lines can be
accurately controlled.
R. Jacson et al., Processing and Integration of
Copper Interconnects from http//www.damascus.no
vellus.com /damascus/tec/tec_03.htm
20Damascene Technology
- Copper interconnect process uses the dual
damascene technology for deposition of copper - potentially reduce the manufacturing cost by
eliminating some labor intensive steps of
aluminum etching. - This makes copper interconnect quite attractive
for semiconductor industry, and positions this
technology as a standard interconnect process for
the most high performance microcircuits in the
future
R. Jacson et al., Processing and Integration of
Copper Interconnects from http//www.damascus.no
vellus.com /damascus/tec/tec_03.htm
21Damascene Technology
double damascene process
Single damascene process
R. Jacson et al., Processing and Integration of
Copper Interconnects from http//www.damascus.no
vellus.com /damascus/tec/tec_03.htm
22Damascene Technology
R. Jacson et al., Processing and Integration of
Copper Interconnects from http//www.damascus.no
vellus.com /damascus/tec/tec_03.htm
23Problems With Copper Metallization
- Major problems with copper metallization
- Copper does not create a passive oxide film (as
aluminum does), - has poor adhesion and high rate of diffusion
through silicon and dielectric layers (organic
and inorganic). - Cu diffuses quickly as an interstitial atom in
the silicon - This introduces new failure mechanisms such as
poisoning of the P-N junctions, charge
instability and formation of resistive shorts
caused by copper electrochemical migration.
R. Jacson et al., Processing and Integration of
Copper Interconnects from http//www.damascus.no
vellus.com /damascus/tec/tec_03.htm
24Barrier Diffusion Layer
- First step is the deposition of a thin layer of
SiN, which acts as a barrier against diffusion of
copper between metal levels. - Deposition of ILD (in this case SiO2) follows the
SiN deposition.
J. Baumann et al., Investigation of Copper
Metallization Induced Failure of Diode Structures
with and without Barrier Layer, Microelectronic
Engineering, Vol 33, pp. 283-291, 1997 , E.
Blanquet et al., Evaluation of LPCVD Me-Si-N
(Me Ta, Ti, W)
25Barrier Diffusion Layer
- Usually high-density plasma methods rather than
traditional PECVD methods are used in deposition
of SiN to obtain dense and pinhole free thin
films with low stress. - In the field of conductive barriers, several
refractory metals and their compounds have been
used, - fundamentally studied including TaSix, TaSixNy
and TaSixOyNx as well as Ti/TiN and TiW
J. Baumann et al., Investigation of Copper
Metallization Induced Failure of Diode Structures
with and without Barrier Layer,
26Comparison of deposition parameters and
electrical characteristics of films
http//ojps.aip.org/aplo/aplcr.jsp
27Inductively Coupled Plasma Generator
J. Baumann et al., Investigation of Copper
Metallization Induced Failure of Diode Structures
with and without Barrier Layer,
28Inductively Coupled Plasma Generator
a). Deposition rate and dielectric constant and
b) Si/C ratio and stress of SiC films as a
function of ICP power
Appl. Phys. Lett., Vol. 81, No. 7, 12 August 2002
29Barrier Diffusion Layer
- Ta and TaNX were found to be best candidates for
the microcircuits with the feature sizes below
0.25 mm - high temperature diffusion of copper decreases
with the increase of nitrogen content
Diffusion Barriers for Cu Metallizations,
Microelectronic Engineering, Vol. 37/38,
pp.189-195, 1997
30Copper Metallization Techniques
- Various deposition methods have been evaluated
for copper metallization - physical-vapor deposition (PVD)
- including plasma sputtering and vacuum arc
deposition - electrochemical deposition (ECD, including
electroplating) - metal-organic chemical-vapor deposition (MOCVD)
31Copper Metallization Techniques
- Conventionally,metal has been deposited by
sputtering. The flux of metal produced by these
methods, however, is not directional enough to
allow the atoms to reach the bottom of very
narrow features - One method of making the flux of metal more
directional is to ionize the metal atoms after
they have been sputtered or evaporated. - Once the have been ionized, a plasma sheath is
used to direct the metal ions perpendicular to
the wafer and straight into narrow openings.
Holber, et al. J. Vac. Science Technology A 11,
2903 (1993)
32Copper Metallization Techniques
- Copper PVD requires seeding and subsequent fill
by the electroplating technique - process of choice to produce void-free fill of
high-aspect-ratio (AR) damascene features - Following the barrier layer, a thin continuous
copper seed layer promotes adhesion and
facilitates the subsequent growth of the bulk
copper fill by electroplating
33Copper Metallization Techniques
- To achieve high filling performance, the incoming
feature profile, seed layer attributes, and key
electroplating process and chemistry parameters
must be optimized to encourage acceleration of
deposition near the base of damascene features
("bottom-up" fill). - The success of copper plating to fill high AR
features is built upon the achievement of
successful nucleation followed by rapidly
accelerated Cu deposition.
34Basic Mechanism of Copper Electroplating
Basic Mechanism of Copper Electroplating
35Normal and defect-generating
- a) smooth seed coverage
- only, metal profile
- following partial fill,
- complete fill by electroplating.
- b) agglomerated seed
- coverage, metal profile
- following some
- electroplating, and resulting
- void at completion of
- electroplating.
Normal (a) and defect-generating (b) via filling
processes.
36Copper PVD
- PVD-fabricated copper seed layer complicates the
formation of void-free copper plugs and lines due
to - relatively poor conformality and bottom/step
coverage of the sputter deposition techniques. - typically in the range of 20 to 40 for
deposition of the diffusion barrier and copper
seed layers in medium to high-aspect-ratio (e.g.
41) via holes and metal line trenches - The void-free filling problem is primarily
associated with the PVD barrier and a seed
deposition overhang thickness profile .
37Copper Metallization Techniques
- The trend in the industry is towards using the
electroplating as the main deposition technique
for copper damascene - Copper deposition is fallowed by CMP.
- Copper CMP is used to remove excess copper and
planarize the surface. - Finally SiN cap layer is deposited.
- wafer is ready for next metallization step.
38Copper Metallization Techniques
- PVD and MOCVD processes allow vacuum clustering
of copper deposition with the barrier/liner and
pre-clean processes. - the ECD methods utilize stand-alone wet
processing equipment.
39Copper ECD process
- Copper ECD processes requires
- suitable diffusion barrier layer (e.g. 100 to
150Å thick layer) - copper seed layer (thickness range of 200 to 800
Å), usually formed by collimated or ionized PVD
and/or MOCVD in a thin-film deposition cluster
tool
40Copper MOCVD
- MOCVD technologies are expected to replace the
PVD-based barrier and copper seed technologies
for copper metallization in scaled sub-0.15/0.13
µm technologies - good adhesion with polymer substrate for
microelectronic - packaging and organic LCD
Joong Kee Lee, Hyungduk Ko, Jin Hyun, Dongjin
Byun , Byung Won Cho and Dalkeun Park Eco-Nano
Research Center, Korea Institute of Science and
Technology
41MOCVD
- MOCVD is possible at room temperature when
periodic negative voltage is applied near the
polymer substrate. - The periodic negative voltage induces ions and
radicals to have nucleation reaction on the
surface of the substrate. - The high efficiency in exciting the reactants in
ECR plasma coupled with periodic negative voltage
allows the deposition of films at room
temperature.
Joong Kee Lee, Hyungduk Ko, Jin Hyun, Dongjin
Byun , Byung Won Cho and Dalkeun Park Eco-Nano
Research Center, Korea Institute of Science and
Technology
42MOCVD
- Metal organic precursor, Cu(hfac)
(1,1,1,5,5,5,-hexafluoro-2,4- pentandione) with
purity 99.9 was heated at 110 oC in a silicon
oil bath, and argon carrier gas conveyed the
evaporated precursor vapor to the substrate. - Cu was deposited by using precursor of hfac(Cu)
TMVS on the ionized PVD TaNx(300Å film) - The TaNx film was deposited on the thermally
grown silicon oxide(1000Å) on the 8 inch bare
Si(100) wafer. - The DC bias that generates periodic negative
voltage is used to induce positively charged ions
on the surface of substrate. - The employed DC bias voltage near the polymer
substrate was fixed at -4kV.
Joong Kee Lee, Hyungduk Ko, Jin Hyun, Dongjin
Byun , Byung Won Cho and Dalkeun Park Eco-Nano
Research Center, Korea Institute of Science and
Technology
43Cluster MOCVD
- Soft plasma clean, MOCVD TaN barrier, and MOCVD
copper seed (and filling) cluster modules - The conformal MOCVD TaN barrier (?70 barrier
conformality) and MOCVD copper seed (? 85-95)
processes enable effective void-free filling of
the holes and trenches using ECD for formation of
inlaid copper interconnect structures.
44Cluster MOCVD
- In cluster MOCVD process, when performed at T?430
ºC - capable of depositing TaN layers with negligible
oxygen contamination, stoichiometric TaN ratio
of 11, ?5 (atomic fraction) carbon
incorporation, electrical resistivities of ?1000
µ? cm, and with over ?80 conformality in high
aspect-ratio structures.
45Cluster MOCVD
a) selective superfilling characteristics in
trenches
b) in via holes of CECVD Cu film
Sung Gyu Pyo, Woo Sig Min, Dok Won Lee, Sibum Kim
and Jeong-Gun Lee Logic Process Development 2,
System IC RD Center, Hynix Semiconductor Inc. 1,
Hyangjeong-dong, Hungdukku,Cheongju-si, 361-725,
Korea
46Cluster MOCVD
Cross-sectional SEM micrographs of highly
conformal TaN diffusion barrier layers deposited
by MOCVD
47Conclusion
- MOCVD copper seed and gap-fill processes have
been integrated with soft plasma clean and MOCVD
barrier (TaN) deposition processes in a
vacuum-integrated cluster tool. - excellent barrier and copper adhesion,
- high degrees of barrier and copper seed
conformality, - low copper resistivity(2 µ? cm), good barrier
integrity - and high-quality interconnect microstructures
have been achieved via cluster-integrated MOCVD
barrier/MOCVD-Cu wafer processing
48Conclusion
- The MOCVD-TaN barrier process presented here
provides superior diffusion barrier properties
and significantly better conformality compared to
the collimated PVD TaN processes. - The thinner MOCVD-TaN barrier layers can be used
compared to the PVD barrier methods, resulting in
higher copper interconnect performance.
49Conclusion
- The integrated MOCVD barrier/MOCVD copper process
is not only a total copper metallization solution
(using MOCVD copper filling) but also can serve
as an enabling technology applicable to ECD
copper filling methods for MOCVD/MOCVD/ECD
formation of the dual-damascene copper
interconnect structures
50Layers Of Copper Interconnects Fabricated
layers of copper interconnects fabricated at IME
11 Science Park Road, Science Park II, Singapore
117685 http//www.ime.a-tar.edu.sg
51Answers
- Q1 Why is copper metal interconnection the metal
of choice for next generation? - copper has a lower resistance (resistivity for
Cu 1.67, for Al 2.66 and for Al-alloys 3.5
?-cm) - Copper has a higher melting point (1083 oC) than
aluminum (660 oC), which leads to greater EM
resistance.
52Answers
- Q2 Why does MOCVD seem to be the technology of
choice for copper metallization - MOCVD technologies are expected to replace the
PVD-based barrier and copper seed technologies
for copper metallization in scaled sub-0.15/0.13
µm technologies - good adhesion with polymer substrate for
microelectronic copper has a lower resistance
(resistivity for Cu 1.67, for Al 2.66 and for
Al-alloys 3.5 ?-cm).
53Thank you
54Reference
- Jon Reid, et al., Copper PVD and
electroplating, Solid State Technology, July,
2000, pp. 86-98. - Rajeev Bajaj,. Copper CMT challenges,
Semiconductor International, June 1998, pp.
91-96. - B.Chin et al., Barrier and seed layers for
damascene copper metallization, Solid State
Technology, September, 1998, pp. 11-13.
55Reference
- Sung Gyu Pyo, Sibum Kim, D. Wheeler, T.P. Moffat,
and D. Josell. J. Appl. Phys. Submitted D.
Josell, Sibum Kim, D. Wheeler, T.P. Moffat and
Sung Gyu Pyo, ECS, submitted. - E.S. Hwang and J. Lee, Surfactant-Catalyzed
Chemical Vapor Deposition of Copper Thin Films,
Chem. Mater., 12, p.2,076 (2000).
56Reference
- J.Lloyd, Electromigration of copper
metallization, Report from Lloyd Technology
Associates, Inc., 1998. - J.Lloyd and J. Clement, Electromigration of
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meeting agenda, Solid State Technology, July,
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reliability, IEEE Electron Device Letters,
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