VLSI Design 1

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VLSI Design 1

• Istanbul Kultur University
• Electrical Electronics Engineering Department
• Fall 2007
• Yard. Doc. Dr. Mustafa Dagtekin
• Lecture 2

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Metal Layers Bonding Pad
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Layout of bonding pad
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Parasitic capacitances
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Pad opening (GLASS CUT)
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Metal-1 Metal-2 Via
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Layout with n-well
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Parasitics
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Capacitance between Metal-1 Metal-2
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Design Rules
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Vias between Metal-1 and Metal-2
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Contact Resistance
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Crosstalk
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Ground Bounce
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Compensating for ground bounce
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Active Layer
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(No Transcript)
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N-select
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Variations
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Variations
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Polysilicon Layer
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Polysilicon
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Polysilicon Self Alignment
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Poly
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Silicide
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Process steps (after n-well formation)
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Process Steps
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Process Steps
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Process Steps
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Metal-Poly Connection
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Substrate Connection
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Laying out n-well resistor
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Laying out NMOS device
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Laying out a PMOS device
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Standard Cell Frames
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Standard Cell Frames
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Design Rules
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Design Rules
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Design Rules
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ESD Protection
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Pad layout
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Layout of a padframe