Interfacing

1
Interfacing

• Real-Time Embedded Systems
• Khalid Abu Muhaimeed
• Nouh Kh.Toolitch
• Supervisor Dr.Loai Tawalbeh

2
Outline

• Interfacing basics.
• Microprocessor interfacing
• I/O addressing.
• Interrupts.
• Direct Memory Access (DMA).

3
Introduction

• Processor process data.
• memory storage
• buses communication
• Communication transfer of data among processors
  and memories.
• This communication is known as interfacing.

4
Basic Terminology

• unidirectional (rd/wr ,
  enable)
• Wires
• bidirectional (data)
• A set of wires with the same function
• a set of wires with a single
  function (data bus).
• Bus
• entire wires collection along
  with their communication protocol.
• Protocol rules for communicating over the wires.
  (low level HW protocols)

5
Basic Terminology

• Port the actual conducting device (metal) on the
  processor (or memory) through which the signal is
  input to, or output from.
• We could use the term pin to refer to a port on a
  processor.
• Pin is also a term referring to the extending
  pins from the processor ( as own IC package).
  They are designed to be plugged into a socket on
  a printed-circuit board.
• Small metallic balls could be used rather than
  pins( if the processor is packaged in its own IC
  ).
• If the processor coexists on a single IC with
  other processors and memories, pads of metal are
  used in the IC.

6
Timing diagram

• 
  
• It is the most common method for describing a HW
  protocol.
• Time proceeds to the right along the x-axis.
• Control lines high or low.
• Data lines (addr, data) invalid (one
  horizontal line) or valid (two horizontal lines).
• The processor must place the address on addr for
  at least tsetup time before setting the enable
  high.
• The high enable line triggers the memory to put
  data on the data wires after tread time.
• When line is active (high, or commonly low) , it
  triggers the data transfer.
• Assert means setting control line to its active
  value.
• Deassert means setting control line to its low
  value.
• A protocol could be consisted of subprotocols
  (i.e. read, write), known as transaction or a bus
  cycle. A bus cycle may consists of several clock
  cycles.

7
Basic protocol concepts

• Actor is the processor or memory involved in
  data transfer.
• A protocol involves two actors a master, and a
  servant (slave).
• A master initiates the data transfer (usually
  general-purpose processor), and the servant
  responds to the initiation request (usually
  memories and peripherals).
• Data direction the direction that the
  transferred data moves btw. actors( receiving or
  sending data).
• Addresses a special type of data used to
  indicate where regular data should go to or come
  from (used to address memory locations ,
  peripherals and peripheral's registers).

8
Time multiplexing

• Share a single set of wires for multiple pieces
  of data.
• Saves wires at expense of time.

9
Control methods strobe and handshake

• A handshake protocol can adjust to a servant with
  varying response times, but it could be slower,
  and need extra clock cycles and extra line.

10
Control methods strobe / handshake compromise

• It achieves both the speed of strobe protocol,
  and the varying response time tolerance of a
  handshake protocol.
• The handshake only occurs if it necessary.

11
The ISA bus protocol Memory Access

• ISA The Industry Standard
• Architecture.
• 80x86 microprocessor.
• 20 bit memory address.
• ALE Address Latch Enable.
• CHRDY Channel Ready.
• Compromise strobe/handshake
• control method is used.
• The memory deasserted
• CHRDY before the rising clock
• edge in C2, causing the
• microprocessor to insert wait
• cycles (up to 6 cycles) until CHRDY was
  reasserted.

12
Microprocessor interfacing I/O addressing

• The microprocessor's pins used to communicate
  data to and from it, are called I/O pins.
• We normally consider the access to peripherals
  (not memory), as I/O.
• Two common methods for using pins to support I/O
  Port-based I/O (Parallel I/O), and Bus-based
  I/O.
• In parallel I/O , a port can be directly read and
  written by processor instructions, like any
  register.
• Ex.P0255, gP2 .
• Ports are often bit-addressable.
• In bus-based I/O, the microprocessor has a set of
  address, data, and control ports corresponding to
  bus lines, and uses the bus to access memory and
  peripherals.

13
Extensions

• Parallel I/O peripheral.
• When processor only supports bus-based I/O
• but parallel I/O needed.
• Each port on peripheral connected to a register
  within
• peripheral. The microprocessor can
  read/write those
• registers.
• Extended parallel I/O.
• When processor supports port-based I/O
• but more ports needed.
• One or more processor ports interface with
• parallel I/O peripheral extending total
  number
• of ports available for I/O.
• e.g., extending 4 ports to 6 ports in figure.

14
Memory-Mapped I/O and Standard I/O

• They are two bus-based methods for microprocessor
  to communicate with peripherals.
• In memory-mapped I/O, peripherals occupy specific
  addresses in the existing address space.
• e.g., Bus has 16-bit address, lower 32K addresses
  may correspond to memory, and upper 32k addresses
  may correspond to peripherals.
• In standard I/O (I/O-mapped I/O), the bus
  includes an additional pin (M/IO), to include
  whether the access is to memory or peripheral.
• e.g., Bus has 16-bit address, all of them for
  memory addressing if M/IO0, and all of them for
  I/O addressing if M/IO1.

15
Memory-Mapped I/O Vs. Standard I/O

• Memory-mapped I/O
• Requires no special instructions
• Assembly instructions involving memory like MOV
  and ADD work with peripherals as well.
• Standard I/O requires special instructions (e.g.,
  IN, OUT) to move data between peripheral
  registers and memory.
• Standard I/O
• No loss of memory addresses to peripherals.
• Simpler address decoding logic in peripherals
  possible.
• When number of peripherals much smaller than
  address space then high-order address bits can be
  ignored
• smaller and/or faster comparators.

16
ISA bus protocol

• ISA bus protocol supports standard I/O.
• The I/O address space is 16 bits, where it is 20
  bits for memory.
• It uses compromise strobe/handshake control
  method.
• similar to memory protocol except address space.

17
A basic memory protocol

• Interfacing an 8051 to external memory
• Ports P0 and P2 support port-based I/O when 8051
  internal memory being used.
• Those ports serve as data/address buses when
  external memory is being used.
• 16-bit address and 8-bit data are time
  multiplexed low 8-bits of address must therefore
  be latched with aid of ALE signal.

18
A complex memory protocol

• Generates control signals to drive the
  TC55V2325FF memory chip in burst mode.
• Addr0 is the starting address input to device.
• GO is enable/disable input to device.

19
Interrupts (interrupt driven I/O)

• Servicing read process data from peripheral
  whenever it has new data.
• Unpredictable
• Polling MP repeatedly check for data
• Simple to implement
• Waste many clock cycles
• External interrupts
• Repeatedly MP checks Int pin after executing
  instruction, if asserted gt jump to ISR
• Pin polling?
• Into MP, done simultaneously with the exec. of
  Instr.
• Maskable vs Nonmaskable Interrupt
• Internal Interrupt (divide by 0,)
• Software Interrupt .

20
Interrupt Addressing

• Fixed Int. ISR address built in MP
• Vectored Int.
• ISR address requested from peripherals by Inta
  pin asserted by MP.
• The address stored in peripheral by extra
  register.
• Interrupt Address Table (compromise between fixed
  vectored)
• Table holds ISR addresses
• Peripherals provide entry number instead.

21
Fixed Int.

1. MP is executing its main program.
2. Peripheral_1 receives input data in a register
   and assert Int to request servicing.
3. After completing Instr. Execution, MP detect Int
   , saves current PC value and set PC ISR fixed
   address.
4. ISR reads Peripheral_1 data processed it, then
   deasserts Int.
5. ISR return, restoring PC and MP resume execution.

22
Vectored Int.
23
DMA

• Buffering temporary storage of data that is
  awaiting processing.
• Using Interrupt
• Storing restoring MP states gt consuming many
  clock cycles (inefficient)
• No execution during data moving.
• I/O of DMA separate single-purpose processor
  (DMA controller).
• Purpose transfer data between memories and
  peripherals

24
DMA flow of actions

1. MP is executing its main program. It has already
   configured the DMA ctrl registers.
2. Peripheral_1 receives input data in a register,
   and asserts req to request servicing by DMA ctrl.
3. DMA ctrl asserts Dreq to request control of
   system bus.
4. After executing instruction, MP sees Dreq
   asserted, releases the system bus, asserts Dack,
   and resumes execution. MP stalls only if it needs
   the system bus to continue executing.
5. DMA ctrl asserts ack reads data and (b) writes
   that data to memory.
6. DMA de-asserts Dreq and ack completing handshake
   with Peripheral_1.
7. MP de-asserts Dack and resumes control of the
   bus.
8. Peripheral_1 de-asserts req.

25
DMA flow of actions (cont.)
26
Arbitration

• Multiple peripherals request service
  simultaneously from single MP or single DMA
• Arbitration decide which one get services.
• Priority Arbiter.
• Daisy-Chain Arbitration.
• Network-Oriented Arbitration Methods.

27
Arbitration Priority Arbiter

• Is a single-purpose processor
• 2 schemes to determine priority among
  peripherals
• Fixed priority unique rank for each peripheral.
  Arbiter choose the higher rank.
• Rotating priority (round-robin) based on history
  of servicing (e.g. least recently serviced)
• More equitable of servicing.

Vectored Interrupt
28
Arbitration Daisy-Chain Arbitration

• Peripherals connected as a chain
• Each peripheral has req. output, ack. input,
  req. input, and ack. Output
• Add or remove peripherals without redesigning the
  system
• Peripherals at the end of chain could become
  intolerably slow.
• Isnt supporting more advanced priority schemes
• If one peripheral stop, the other lose access
• Each peripheral must be daisy-chain aware
• Otherwise, external logic is used.

29
Arbitration Network-Oriented

• Multiple MP connected by a shared bus (network).
• Arbitration among processors.
• Typically built right into the bus protocol
• The protocol must ensure that no contending
  processors sending at the same time
• Examples I2C, Ethernet, CAN

30
Multilevel Bus Architectures

• Numerous type of communications
• Most frequent and high speed (between MPs).
• Less frequent and low speed (between MP and
  Peripherals like UART)
• Single high speed bus
• Required each peripheral to have high-speed bus
  interface
• Extra gates ,Power consumption and cost.
• May not be very portable.
• May result in slower bus.
• 2 level buses
• Processor local bus connects MP, cache, memory
  controllers
• Peripheral bus ISA, PCI
• emphasize portability, low power or low gate
  count.
• Bridge (single-purpose processor) connect two bus
  levels

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Multilevel Bus Architectures cont.

• 2 level buses VSI Alliance.
• Processor local bus
• System bus
• Peripheral bus

32
Advanced Communication Principles

• Physical layer the medium that is used to carry
  data from one device to another.
• Single wire, a set of wires, radio waves, or
  infrared waves.
• Parallel communication
• Serial Communication
• Wireless Communication

33
Parallel communication

• Multiple data wires control and possibly power
  wires.
• Each wire carries one of the bits.
• High data throughput, if the length is short.
• Long parallel wires
• High capacitance values gt more time to charge or
  discharge
• Misalignment.
• Costly to construct.
• May be bulky
• In general, used when connect devices reside on
  the same IC or circuit board.

34
Parallel Protocols

• PCI (Peripheral Component Interconnect)
• Originated at Intel 1990 and then administered by
  PCISIG
• First used in 1994
• For interconnecting chips, expansion boards,
  processor memory subsystem.
• Replaced ISA/EISA bus
• Transfer rate 127.2 508.6 Mbit/s
• 32-bit addressing later extended to 64-bit
• Sync bus architecture
• ARM
• Designed by ARM Corporation
• Designed to interface with ARM line of
  processors.
• 32 data/address
• Sync data architecture
• Transfer rate not specified (function of the
  clock speed)

35
Serial communication

• Single data wire, along with control possibly
  power
• Higher throughput than parallel when connect
  distant devices
• Less average capacitance.
• Cheaper to build
• More complex interfacing logic communication
  protocols (compose decompose data)
• Most protocols use same wire for control
• Start bit
• Stop bit
• May use additional wire for clocking purpose as
  sync tech.

36
Serial Protocols

• I2C (Inter-IC)
• Developed by Philips Semiconductors
• 2 wire bus protocol
• Connect peripheral ICs in electronic systems
• Transfer rate up to 100 kbit/s, 7-bit address
• Fast mode 3.4 Mbit/s, 10-bit address
• Flash, RAM, EPROM, Microcontrollers
• CAN (Controller Area Network)
• For real-time application
• Developed by Robert Bosch GmbH to connect various
  components of car
• Over twisted pair of wires
• High integrated serial data communication
• Data rate up to 1 Mbit/s
• 11-bit addressing
• Documented in ISO 11898 ISO 11519-2
• Common applications Automobiles, elevator
  controllers, copiers, telescopes,

37
Serial Protocols

• FireWire (I-Link or Lynx)
• Developed by Apple Computer Inc.
• Specification is given by IEEE 1394
• Mass information transfer
• Transfer rate 12.5 400 Mbit/s
• 64-bit addressing (64b net id, 6b node id, 48b
  mem addr)
• Real-time connection and disconnect and
  assignment (Plug and Play)
• Designed for interfacing independent electronic
  devices.
• USB (Universal Serial Bus)
• Has 2 data rates 12 Mb/s, 1.5 Mb/s
• For PC users to connect monitors, printers,
  scanners,
• Used tiered star topology (USB hubs)

38
Wireless communication

• Physical layers
• IR
• Relatively cheap
• Need line of sight
• Diode emits infrared light to generate signal,
  Infrared transistor detects signal.
• RF
• Line of sight not necessary
• Longer distance communications
• Frequency hopping, to communicate while
  constantly changing transmission frequency.

39
Wireless Protocols

• IrDA (Infrared Data Association)
• IrDA is an international organization
• Designed to support transmission between two
  devices over short-range point-to-point infrared.
• Rate 9.6 Kb/s 4 Mb/s
• Deployed in notebooks, printers, PDAs, cell
  phones,
• MS Windows CE 1.0 the first Windows OS support it
• Available on several popular embedded OSs
• Bluetooth
• Use radio frequency
• Within 10 meters
• Doesnt require a line-of-sight connection
• IEEE 802.11
• IEEE proposed standard for WLAN
• Ad-hoc vs. infrastructure
• PHY and MAC layers
• Data rate 1Mbps, 2Mbps
• Calls 2.4 2.4835 GHz frequency band
  (unlicensed band).
• Use CSMA/CA
• Signals for transmission RTS, CTS, and ACK.

40
Reference

• Embedded system Design A unified
  Hardware/Software Introduction, Frank Vahid,
  Tony Givarrgis, Wiley, 2002

41

• Questions?