Virgo

1

• Virgo
• Control Electronic upgrade
• Annecy/Pisa/EGO
• B.Mours

2
Post C6 upgrades (I)
3
Current main Virgo control loop

• Frequency 10 kHz?100µs
• 30 VME crates for this loop
• Main limitations
• Old hardware (10 years old)
• DSP and CPU performances
• Time is shared between
• Computing
• Interrupt response
• Data access (on VME bus 3-4 words/µs 3 µs)
• Input, Output, Monitoring
• fitting complex filters or algorithms ?
• Delay (distributed system) AR FilterPrGCScFil
  ter ? 500 µs
• Impact on the loop bandwidth
• Sampling rate of the dark port and monitoring
  channel (20kHz)
• Fast readout could be useful for debugging
• Analog servo for the frequency stabilization

4
Redesign of the control Electronic

• Increase
• Computing performances new DSP and CPU
• Data throughput new DOL
• gain a factor 10 100Mbits/s ?1 Gbits/s)
• Lower Noise New ADC, DAC, differential
  connection (ADC, timing)
• More channels more compact electronic
• New timing system
• To be interfaced to the new boards
• distribute the GPS signal simpler
• A possible goal for the main loop 60 kHz
• 1/60k16us Arm length
• Will increase the DAQ rate
• Now 18 MB/s (6-7 MB/s of compressed data)
• Front end, preprocessing, data transport, storage

5
New processing board

• Replace 5 VME boards by 1
• 1 VME CPU? PC 104 or PC on PMC
• 2 Digital Optical Link1 Timing ? TOLM
• 1 DSP board ? DSP mezzanine
• To be used by Pr, GC, Sa, Sc
• Payoff Integrated DAQ (frame building)

6
New DSP Mezzanine

• 1 DSP _at_ 60 MHz (60 MFLOPS peak)
• ? 6 DSPs _at_ 100MHz (ADSP211160N SHARC DSP 3.4
  GFLOPS)

7
MDSPAS Top View

• A prototype exist since a few weeks

8
TOLM

• TOLM
• Timing and Optical Link Mezzanine
• Interfaces
• PCI interface for configuration and tests
• TIMING part
• 1PPS and GPS on differentiel link (one single
  cable RJ45)
• Changed to IRIG-B on coax cable fibers.
• 1 Serial link to DSP for GPS time info
• 2 front panel output for pulses
• 2 DPS output for pulses
• Digital Optical Link part
• 2 input and output fibers
• Monomode or multimodes
• Higher data rate 155Mbits/s ? 1GBits/s
• 4 DSP links (PCI-J4)
• Status
• Prototype available since last September
• Developing the FPGA software and testing.

9
Timing generation

• The TOLM use always a local oscillator (TCXO)
• The local oscillator will be lock on a GPS
  reference
• Need
• Distribution of GPS clock absolute timing
  information IRIG-B
• Selection of clock and distribution boards
• In progress

IRIG-B
IRIG-B
GPS Antenna
TOLM
Fiber to coper
IRIG-B
Copper to Fiber
CommercialGPS Clock
3.3 Km max.
3 m max
Optic Fibers
Coax cable
10
Optical Link Extension board

• Need Fan-out board in the case of
• Global control connections
• Multiple Pr/ADC input
• Multiple inputs(8)/single output
• Single input/ Multiple outputs
• Need simple protocol to route the data
• Development started

11
New ADC/DAC

• New ADC
• More bits (18?)
• Faster sampling rate (100 kHz 1 MHz)
• Input compression (whitening) filters
• On board decompression option
• Low noise Optical link to processing boards
• Include (part of) the TOLM design for timing
  generation?
• Versatile enough to reduce the number of ADC type
  (Currently 3).
• New DAC
• Need of a very high dynamical range for
  actuators.
• The DAC board used has -98 dB of total harmonic
  distortion noise
• while newer chips are available on market with
  120 dB
• Two different design approaches are under
  evaluation
• Standard VME board, 16 ch. 24bits (nominal)
• Distributed system
• Status
• Early design phase (selecting the main components)

12
Conclusion

• Development of the new control system is in
  progress
• It will be a MAJOR change for Virgo
• Hardware and Software
• Probably several weeks of down time in 2007 (?)