Dr Richard Reilly

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Lecture 8

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• Dr Richard Reilly
• Dept. of Electronic Electrical Engineering
• Room 153,
• Engineering Building

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RISC vs. CISC

• Accuracy of these architecture designs can be
  seen in the following example
•  

• CISC Motorola MC68000
• contains 200,000 transistors,
• 10 person years of design effort
• achieves a performance of 2 MIPS.

• RISC ARM Processor
• contains 27,000 transistors,
• 6 person years of design effort
• achieves a performance of 5 MIPS.
•  

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RISC vs. CISC

• RISC removes redundant instructions from the
  instruction set
• Þ Remaining instructions can be executed much
  more rapidly than was previously possible.
• Þ Improved performance overall.

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RISC vs CISC

• The goal of the RISC designer to reduce the
  complexity of the instruction set
• all single cycle - single word instructions.
•  
• Better for microprocessor to just provide only
  those frequently used instructions and make them
  very fast.

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RISC vs CISC

• Two disadvantages
• Faster execution of instructions requires faster
  memory access.
• Equivalent functionality requires more
  instructions (and hence more memory) because each
  individual instruction is simpler.

• Disadvantages no longer highly significant
• memory densities and speeds have increased.
• Þ RISC approach outweighs disadvantages.

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Parallel Processing

• The problems of memory access etc. are sometimes
  described as the Von Neumann bottleneck.

Try to do things in parallel !!

• Main objectives in parallel processing
• Divide up processing up into subtasks
• Performed/execute these subtasks in parallel
• Hence much faster

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Parallel Processing
Parallel Processing requires

• Hardware is configured to support this
  parallelism.
• Software capable of recognising and suitably
  subdividing potentially parallel processes into
  their subordinate elements
• Communications between elements is far from
  trivial and are the subject of much research.
•  

• Pipeline architecture thus eliminates
  inefficiency of an idle ALU
• fetches the next instruction while current one
  is executing
• provides concurrent operation.

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Sequential Mode of Operation
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Pipeline Architecture How ?

• Need a data storage register between memory and
  CPU.
• Increases processor throughput by reducing idle
  time from the
• sum of the system component set-up and
  propagation delays
• to the
• worst case delay of the slowest element in the
  pipeline

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Pipeline Architecture

• Pipeline mode of operation

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General Purpose Architecture
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General Purpose Architecture

• Keyword here for this processor is general
  purpose .
• 16-bit or 32-bit design
• hardware design of a microprocessor CPU is
  arranged so that a system can be configured
  around the CPU as the application demands.
• The prime use of a microprocessor is to
• fetch instruction
• fetch data
• execute the instruction
• display and store the result
•  

• This is OK for general applications

• For special applications.there are alternative
  designs

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Harvard Architecture

• Digital Signal Processing
• Speed of data manipulation are key issues for
  real-time performance.
•  

• Use of Harvard Architecture is employed for DSP
  hardware processors.
• characterised by the separation of program memory
  and data memory.
• the use of separate address and data buses for
  both program and data memory,
• thus data fetches can be concurrent with the
  fetching of the next program instruction. i.e.
  pipelining

• Compared with conventional microprocessors the
  most striking feature is the use of parallelism
  and pipelining to improve speed.

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Harvard Architecture

• DSP involves multiplication of data with
  pre-computed coefficients.
• Harvard Architectures perfect for this process

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