dsPIC MathDemo's

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dsPIC MathDemo.s

• CTEC1631/2009F

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Simple Multiply mul.ss

• W0 contains 256 (0100H the multiplicand)
• W1 contains 66 (0042H the multiplier)
• W4 contains the product 256 66 16896 (4200H)

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Modified Simple Multiply

• If W0 instead contains 4096 (1000H)
• After the mul.ss, W5W4 contains the product
  0004H2000H 42000H (270,336) a 32-bit product

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DSP Multiply - mpy

• Use Accumulator A for the product
• Note that w6w7 is one of the usable register
  combinations (w0w1 cannot be used)
• The accumulators are 40-bit (ACCAUACCAHACCA or
  ACCBUACCBHACCB)

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DSP Square - mpy

• Use Accumulator A for (w6)2
• Note that the clr instruction at line 63 is
  unnecessary, since the mpy instruction will
  simply overwrite the contents of A

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Multiply and Accumulate mac (0)

• Before the MAC, W4 contains 4, W5 contains 3, and
  A has been cleared
• The MAC operation is equivalent toA A W4
  W5

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Multiply and Accumulate mac (1)

• After the first MAC, A contains 12
• Both MACs are equivalent to
• A 2 W4 W5which we expect to be 2 4 3
  24

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Multiply and Accumulate mac (2)

• Next, use the barrel shifter to do a right shift
  of 2, which is equivalent to a divide by 4A (
  2 W4 W5 ) / 4 ( W4 W5 ) / 2so we expect
  the answer to be ( 3 4 ) / 2 6

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Barrel Shifter - sftac

• The sftac instruction can shift up to 14 bits at
  a time (the size of the barrel shifter).
• Note that sftac will shift bits from ACCAU and/or
  ACCAH into ACCA, if necessary.

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Multiply and Accumulate mac (3)

• MAC supports prefetching, which allows it to
  set up arguments in anticipation of another MAC
  call
• This can be done in one clock cycle!
• After this MAC, A contains the expected answer (4
  3 12), but the contents of W5 have already
  been replaced by the contents of W0 (256), and W8
  has already been post incremented to 2 (from
  zero).

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Multiply and Accumulate mac (4)

• If another MAC instruction is added, A now
  contains 4 3 4 256 1036.
• The next MAC instruction will add in 4 66 the
  66 was prefetched from W2 (W8 had previously
  contained 2 and was post incremented to 4).