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Device scaling laws
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Interconnect scaling laws
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Example Al and oxide technology

• Typical scaling factor over 4 years are
• S0.6, f2, D1.3,
• Since the metal and the dielectric materials are
  the same
• rloc2/3, r1, k1.

• The intrinsic gate delay drops by a factor of 0.6
• The local interconnect delay drops by 2/3
• The global interconnect delay increases by
  krD2/S24.69

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Example Switching to Cu and low-k technology

• Typical scaling factor over 4 years are
• S0.6, f2, D1.3,
• The metal and the dielectric materials have been
  changed,
• The local interconnect technology has not
  changed
• rloc2/3, r1/2, k1/2.

• The intrinsic gate delay drops by a factor of 0.6
• The local interconnect delay drops by 1/3
• The global interconnect delay increases by
  krD2/S21.17

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The signal propagation effect

• The signal can not propagate faster than the
  speed of the electromagnetic wave Vc

• The speed of the electromagnetic wave Vc is
  proportional to 1/(LC)1/2

The inductance L is constant while the
capacitance is proportional to k. Therefore
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Effect of scaling on Timing

• Clock frequency increases
• The global interconnect delay becomes dominant
• Coupling capacitance becomes important
• Inductance becomes an issue
• Clock skew variations limits the clock frequency

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Gate and Interconnect delays
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Effect of scaling on noise
1. Cross talk - signal propagation to neighboring
wires 2. Simultaneous switching noise on the
power line 3. Charge sharing effects - affects
mostly dynamic logic 4. Leakage current - affects
DRAM and switch capacitor filters.
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Effect of scaling on the power
1. Higher frequency - higher power dissipation
(P) 2. Lowering VDD is a solution - limited by
noise margins. 3. Higher capacitance increases
P 4. Lowering threshold improves margins but
increases the leakage current 5. Higher CMOS
transition current and dissipation
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Effect of scaling on the reliability
1. Higher power per unit area --gt higher working
temperature 2. Higher current density --gt higher
electromigration 3. Higher interconnect stress
levels --gt stress voiding
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Interconnect models

• Resistors

Rr L/A
At higher frequency the skin effect reduces the
interconnect cross section. The skin depth, d, is
defined by the penetration distance at which the
current density drops by 1/e
Where f is the frequency, r is the resistivity
and m is the magnetic permeability
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Interconnect models

• Capacitors

Ce0er A/d

• Inductors

Inductors are more difficult to calculate. Some
models will be described I the next lecture.