MultiNoC

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MultiNoC
Multiprocessing System Enabled by a Network on
Chip
alinev_at_inf.pucrs.br moller_at_inf.pucrs.br carara_at_in
f.pucrs.br
Aline Vieira de Mello Leandro Heleno
Möller Everton Carara
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MultiNoC

• What is it?
• a programmable on-chip multiprocessing platform
• network-on-chip (NoC) used as communication
  mechanism
• Why use it?
• demonstrate that NoCs can be used in FPGAs
• demonstrate that parallel applications can be
  easily prototyped.
• What goal to address?
• industrial applications requiring high bandwidth
  and/or parallel processing NoCs are better than
  buses
• academic - undergraduate/graduate advanced
  computer architecture disciplines

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MultiNoC Architecture

• NUMA architecture
• each processor has a local memory and may access
  other processors (remote) memories
• wait/notify instructions to synchronize IPs
• avoids deadlock or indefinite postponement
  situations

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MultiNoC Synthesis
Chip Constrained Floorplan

• Occupied Slices 2,325 out
  of 2,352 98
• Number of 4 input LUTs 3,699 out of
  4,704 78
• Number of Block RAMs 12 out of
  14 85

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MultiNoC System Flow Diagram
Spartan-IIE
R8 Simulator
Application
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MultiNoC Demo Application

• Application 1 Parallel edge detection
• Host computer sends an image line
• Each embedded processor computes one gradient (gx
  and gy)
• One embedded processor adds gx and gy and
  notifies the host
• Host receives processed line and sends a new line

• Application 2 Parallel Sort