Challenges in the 21st Century DSP Technologies

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Challenges in the 21st Century DSP Technologies

• Lajos Gazsi
• Infineon Technologies
• FTW, Telecommunications Forum
• Vienna, 23rd March 2001

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Outline

• Role of Digital Signal Processing
• Silicon technology challenges
• Design Time
• Power Dissipation
• Clock Interconnect Delay
• I/O- Memory Bandwidth
• Noise Margin
• Algorithm design challenges
• Consequence for Mobile, Internet and Broadband
  Multimedia market
• OSI-Reference Model three computing engines
  (MPU, Protocol, DSP)
• Conclusions

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Triumphal procession

• Digital signal processing
• takes by storm more and more applications
• down scaling speeds-up its triumphal procession
• e.g at 0.18 µm R/W - channel (disk
  driver) chip

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Santa Cruz Read Write Channel
Technology 0.18 mm (C10N) Transfer Rate 850
Mbit/s Package P-TQFP-100 Analog Area 20
(relative) Digital Area 80 (relative)
Design partly with Datapath Generator
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VLSI Digital Signal Processing

10 100 1k 10k
100k 1M
Pipelined Systolic Arrays
VDSL
Cable Modem
Analog
time
Number of arithmetic operations per sample
Signal- Processor
ADSL
R/W channel
VoIP
VB Modem
Microprocessor
1 Hz 100 Hz 10 kHz
1MHz 100 MHz 10 GHz
Analog-Signal-Bandwidth
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Trends in VLSI-Technology Computational Power
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Source T. Noll RWTH Aachen
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Advantages of digital signal processing

• Well known benefits of Digital Signal Processing
• no temperature drift, no aging effects
• no manufacturing tolerances, better yield
• simpler technology change
• better simulation possibility
• better reproducibility
• resource sharing is possible
• can easily be made adjustable or adaptive
• intelligent solutions are possible
• (e.g. voice activated chip, results of brain
  research, artificial human-based control,
  combining of different sensor readings, etc.)

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Present of digital signal processing

• DSP Chip Market by Type
• Programmable DSPs 39.5
• Function-Specific DSPs 56.6
• Media Processors/MPUs 2.9
• Source Will Strauss, IEEE Signal Processing
  Magazine (March 2000)
• Future
• 29.3 compound annual growth rate from 1999
  through 2004
• Source Dataquest (May 2000
  Estimates)

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Driving forces for Mobile, Internet and Broadband
Multimedia

• Digital Signal/Protocol/Control Processing
• Marketing
  Technologies
• social and business landscape
  microchip design
• today
  
• voice dominated market
  CMOS technology
• future
  Algorithm design
• multimedia IP-based market
• with intelligent solutions
  
  

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Challenges of Mobile, Internet and Broadband
Multimedia

• Challenges of DSP design
• Challenges of CMOS design
• Challenges of algorithm design
  

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CMOS technology -gt SIA roadmap
99 02 05 08
11 14
180 130 100 70
50 35 nm
1G 8G
64G
1250 2100 3500 6000
10000 13500
500 700 900
1200 1500 1800 ASIC
2304 3042 3042 3840
4224 4416
90/1.4 130/2 160/2.4
170/2 174/2.2 183/2.4
450 567 622 713
817 937
1.8/1.5 1.5/1.2 1.2/0.9
0.9/0.6 0.6/0.5 0.6/0.3 max/min

Source Semiconductor Industry Association, Stand
1999
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First Design time problem

• Two contradictory tendencies
• design complexity grows significantly
• time to market has to be reduced
• in the past help
• hardware description languages (VHDL, Verilog)
• high level tools (Matlab, COSSAP, SPW)

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Second Power dissipation problem
99 02 05
08 11 14
90/1.4 130/2 160/2.4 170/2
174/2.2 183/2.4
1250 2100 3500 6000
10000 13500
500 700 900 1200
1500 1800 ASIC
1.8/1.5 1.5/1.2 1.2/0.9 0.9/0.6
0.6/0.5 0.6/0.3 max/min

where
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Third Clock Interconnect delay problem
99 02 05
08 11 14
450 567 622 713
817 937
1250 2100 3500 6000
10000 13500 500 700
900 1200 1500 1800

Chip size, on-chip clock increasing
Problem physical design
Source Semiconductor Industry Association
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Fourth I/O Memory Bandwidth problem
99 02 05 08
11 14
2304 3042 3042 3840
4224 4416
1250 2100 3500 6000
10000 13500 uP
500 700 900 1200
1500 1800 ASIC

I/O number, on-chip clock increasing
Problem memory bandwidth
Source Semiconductor Industry Association
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Fifth Noise margin problem
99 02 05 08
11 14
1.8 1.5 1.2 0.9
0.6 0.6 max
1.5 1.2 0.9 0.6
0.5 0.3 min

Power supply voltage decreasing
Problem noise margin
Source Semiconductor Industry Association
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Challenges in algorithm design

• Algorithms
• unpredictable history combining evolution with
  revolution steps
• e.g. FFT, Viterbi decoding, Huffman, Reed Solomon
  coding, etc
• similar rule as Moores Law doesnt exist
• challenge
• find an appropriate measure to specify algorithm
  efficiency
• optimality of an algorithm
• silicon friendly implementation
• locality, regularity, massive parallelism,
  robustness
• memory (RAM/ROM) requirements

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Consequence for Mobile, Internet and
Broadband Multimedia
OSI-Reference Model
Main topics
File Transfer, Email, WWW, Terminal Emulation,
VoIP, Video Conference, E commerce, etc.
Interpretation, Encryption, transformation Orderin
g, Synchronization, Managing of session
Data, Voice, transport without errors, losses,
duplications, in the right order (TCP,UDP)
IP, ARP, ICMP, protocols to communicate, to
link, to address, for sequence , flow and error
controlling
Ethernet, FDDI, Token Ring
Data, voice through media as copper wires,
coaxial cable, optical fiber, radio
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Different type of processing engines

• Microprocessor/Microcontroller
• managing of user-interface, operating system,
  flow control
• mask-able interrupts, asynchronous events,
  control flow,
• encryption, integer arithmetic, memory management
• Protocol (network) processor
• synchronous events, parsing, head processing,
  multiplexing,
• I/O management, flow control, error controlling,
  multithreading
• Digital signal processor
• ... self-contained computing engines with
  superior math capability and architecture better
  suited for processing a digital signal stream
  Will Strauss, IEEE Signal Processing Magazine
  (March 2000)
• computing error are interpreted as noise
  contributions noise floor,
  overflow limit gt signal/noise value
  computing precision is
  permanently checked by S/N values

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Behavior of digital signal processors

• Execution of algorithm (computing it)
• produces errors (overflow, underflow)
• ? S/N will be smaller.
• In order to keep the decrease of S/N to an
  allowed level,
• the internal word length has to be enlarged.
• more bits at LSB side ? rear bits
• more bits at MSB side ? guard bits
• using scaling operations, where they are
  appropriate
• embedding procedures in ASICS

To manage S/N there are four screws rear bits,
guard bits, scaling operations and noise shaping
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Managing S/N in DSPs

• For fixed point digital signal processors
• more bits at the LSB side ? full precision
  multiplication
• (double word special registers, often is not
  available at µP, µC)
• more bits at the MSB side ? longer ACCUs
  (special registers)
• as required from multiplication
• (place for overflow bits)
• scaling operations ? special hardware in
  execution units saturation, shift at
  input/output
• of ACCUs, rounding mechanisms.

DSPs are Bavarian castles with a lot of
decoration, since they have to manage S/N values.
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Vertical Integration Terminals
Processing engine with high level compiler (C,
C, Java, or ???)
OSI-Reference Model
Microprocessor
Protocol Processor
Heterogeneous Architecture HF,
Analog, DSP, Control
Strategy System-on-a-chip realization because of
silicon area critical parameter power dissipation
(also leakage)
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Future processors at terminals

• 3G requirements not possible as SW with current
  DSPs
• Dedicated HW signal processing programmable
  DSPs
• Value added capabilities like
• speech recognition, noise suppression, video
  codecs, etc.
• Focus on low-power active and standby (efficient
  power man.)
• Re-configuration and re-programmability
• Ease of use room for innovations
• Focus on tools and development methods
• Processor Convergence RISC/ARM DSP World

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Horizontal Integration in the Network
OSI-Reference Model
Multi-channel integration
Microprocessor
Protocol Processor
Heterogeneous Architecture HF, Analog, DSP,
Control
Strategy efficient realization (area reuse per
multiplexing by channel) careful
partitioning between ASIC/programmable engines
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Three engines will remain the driver

• Increasing audio, video, and graphics capability
• gt DSP and Vector processing
• Connectivity (content and data,switching/routing/t
  ransmission)
• gt Protocol (network) processor
• New services (with voice activated, multimedia
  packet-switched technology with intelligent
  solutions)
• gt Real time operating systems MPUs, MCUs

In both cases (Terminal, in Network) memory
dominant eDRAM Carefully optimization
between software/hardware solutions Different
optimum Terminal new engine with DSP, Protocol,
MPU capability or in Network
hardware/software co-design
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Design time problem

• Hardware description languages
• VHDL, Verilog (Direct synthesis)
• High level tools (Matlab, COSSAP, SPW)
• But with down scaling it comes to life again
• New design flow (compiling directly from C,
  Open SystemC)
• reuse of soft macros, firm macros, IPs, Virtual
  Socket Interface
• internet companies
• Platforms for different application areas
• Platform a family of personalized products using
  the same hardware through several technology
  steps utilizing re-configuration and
  re-programmability (e.g. 4G wireless, VPN, VoIP,
  automobile, etc.)

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Hardware/Software Partition

Overall Cost
New platform
100 Hardware
100 Software
Partitions Law the overall cost optimum is
always moving with new
technologies toward software realization. Coroll
ary the design will become more and
more memory
(RAM/ROM) dominant memory optimizing compilers.
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Power dissipation problem

• Mature low-power design techniques
• Vdd reduction is the most effective method
• highly parallel and pipelined architectures
• reduction of switching factor and glitches
• reduction of node capacitances
• (preserve locality in algorithm design)
• proper number representation
• Bob Brodersen, T. Noll, Chandrakasan, Rabaey, etc

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I/O and memory bandwidth problem

• System on chip
• hybrid, heterogeneous, embedded systems
• memory DSP, RISC, µC Kernel, Datapath SIMD with
  Cache, embedded FPGA, HF, mixed signal, sensors
• Memory embedded DRAM, SRAM, FRAM
• highly pipelined
• wide busses between modules
  

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Clock Interconnect delay problem
System
100 Functions
VHDL
1000 Objects
Physical design problem
Synthesis
1 000 000 Gates
Layout
10 000 000 Transistors
One cycle long time connection is limited only
to a small portion of the chip area
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Clock interconnect delay problem

• Modified design flow
• meeting in the middle
• simultaneously start of algorithm and physical
  designs
• methods for preserving locality and regularity in
  layout
• firm macros (soft macro layout information
  in script)
• T. Noll (University Aachen)
  Datapath Generator
• FPGA realization for low volume

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Optimal operating rates in DSP chips

• Optimal choices for rates in silicon
• oversampling rate proper for A/D, D/A Sigma Delta
  converter or high frequency interfaces
• optimal technology operating rate for good
  silicon efficiency (area, power, throughput rate)
• information rate given by spec

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Noise margin problem

• Introduce redundancy in order to enhance
  reliability
• system level (see communication networks)
• module level (e.g. voting circuits)
• number representation level (e.g. residue number)
• circuit (gate, transistor) level

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Challenges of DSP technologies

• Design time problem
• originated from early days and it remains a
  challenge
• Software and hardware partition problem
• codesign remains a challenge
• Power dissipation problem
• it comes to life in the early nineties and it
  remains a challenge
• Clock Interconnect problem
• it faces us now (new design flow FPGA)
• I/O and memory bandwidth problem
• it will sharpen soon (embedded heterogeneous
  systems)
• Noise margin problem
• it will follow after about year 2005
  (redundancy)

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Conclusion

• Digital Signal Processing thanks
• to CMOS technology success and
• to the advance in algorithm design
• will follow its triumphal process in the next
  decade!

and after it ???
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