ART 200

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ART 200
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The challenge

• New generation devices grow in complexity
• Identifying all defects through a quick burn-in
  is no longer a choice
• Devices incorporate multiple functions
• Test fixtures and software grow more expensive,
  actual test time takes longer
• Complex testers drive large engineering and
  capital costs

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The answer Highly Parallel Intelligent Final
Test

• High Performance Reliability Testers
• Programmable Testers for fully customized
  solutions
• On-line monitoring of input and output signals
• Standardized environment for test flow and data
  output (same in development and production)
• One tester covers all devices and all functions

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Test costs are increasing with the reduction in
feature size
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Reliability Test Challenges
Thermal Run-away
These challenges dramatically increase costs

In some cases test is not feasible by using
traditional approach
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Design For Test The Way-Out

• DFT support for straightforward device management
• Makes feasible reliability testing (IO count
  reduction, PLL ..)
• Reduces operation cost (equipment, board)
• DFT support for increased visibility
• Reduces process cost
• Test During Burn In
• Batch Testing
• Increases yield through on-line defect
  classification
• Enables straightforward device qualification by
  continuously testing devices during stress

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ART 200
Very broad Device Coverage
Very broad Application Coverage
Supports all DFT Methodologies
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ART 200

• Scan chain
• JTAG
• BIST
• SOFT-BIST

Supports all DFT Methodologies
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ART 200

• General digital logic
• Micro controllers
• Mixed-signal, analog
• Non-volatile memories
• RAM
• Multimedia
• Multi-chip
• Embedded memory
• 0.8 V Vcc
• Medium power

Broad Device Coverage

• System-on-chip

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ART 200

• Final Testing
• Batch Testing
• Test During Burn In
• New Product / Process Qualification
• Endurance Cycling
• Life Test
• Reliability Test in Manufacturing
• Intelligent Burn In

Broad Application Coverage
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Features

• One Driver per slot architecture
• Extremely fast test pattern download
• Compatible with very low voltage (0.9 V) devices
• 6 independent power supplies, up to 75 A per slot
• 288 IO channels
• Vectorial stimulus/monitoring and algorithmic
  device management
• 50 nsec vector time, 25 nsec edge placement, all
  common vector formats
• Complete functional test flow implemented for
  back-end testing of stand-alone and embedded
  memories
• Analog function generator and monitoring

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Driver Architecture CPU

• CPU
• 220 MIPS MCF 5407
• Kernel
• Hardware Supervision
• Test Program (User)
• DUT Management (User)

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Driver Architecture POWER SUPPLIERS

• PROGRAMMABLE POWER SUPPLIES
• Independently programmable on each driver
• 6 channels, any combination of
• -20 .. 20 V 12.5 A 60 W
• -100 .. 100 V 6 A 60 W
• 50 mV precision on the device in the low
  voltage range
• Alarm monitor on voltage and current
• 6 reference voltage channels with optional
  current measurement possibility

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Driver Architecture PROGRAMMABLE LOGIC

• PROGRAMMABLE LOGIC
• 600 K Gate
• 170 MHz
• Application Specific IP
• Vector Sequencer
• Memory
• Custom

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Driver Architecture VECTOR SEQUENCER

• VECTOR SEQUENCER
• 50 nsec vector time
• 25 nsec edge placement
• Formatting on 16 channels
  (NRZ, RTZ, RTO, SBC)
• 32 Mvectors on 64 channels
• Configurable (16 M on 128, )
• Extendable to 64 M
• Configurable monitoring
• 32 stimulus 256 monitor 256 / 32
• Up to 256 devices 256 monitored lines
• Segmentation
• Real-time switch between segments
• Run-time pattern reload

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Driver Architecture VECTOR DATA AND MEMORY

• VECTOR / DATA MEMORY
• 32 M x 64 (64 M x 64
  optional)
• 50 nsec Access Time

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Driver Architecture PIN ELECTRONICS

• PIN ELECTRONICS
• 288 channels
• 8 clock
• Tri-state and i/o programmable in group of 8
• Vih range 0.8 .. 6.5 V 50 mV precision
• Vil lt 0.3 V
• 400 mA output current on 16 channels, 100 mA on
  the remaining ones
• High voltage on 184 signals

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Driver Architecture ANALOG MODULE

• ANALOG MODULE
• 4-channel Function Generator
• Standard Waveforms
• Programmable Offset, Frequency, Amplitude
• AM and FM Modulator
• Static Monitor 0..5 V Range

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Driver Architecture TEST BOARD CONNECTORS

• TEST BOARD CONNECTORS
• 540 edge contacts
• 3 A each
• 125 V isolation
• 10 m? contact resistance
• 6060 kg insertion force
• 2000 insertions

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User Benefits (1)

• Test feasibility
• DFT support
• SOC features (memorylogic, memorymixed-signal)
• Non-deterministic timing or value
• Cost saving
• Lower operation cost exploiting DFT features
• Lower process cost with TDBI and Batch Testing
• Better time-to-market
• Unique environment for every reliability and
  functional testing operation

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User Benefits (2)

• Increased yield
• Higher visibility on the devices
• Detailed reliability data generation
• Higher outgoing quality
• Increased stress through DFT
• Investment optimization
• Best equipment utilization (wide device family
  coverage)
• Long-term investment (standardized DFT-based
  device management)

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• The first ART 200 production system in the USA

will be installed November 02
at ISE Labs. Fremont CA
You are cordially invited for a personal demo on
September 19, 20, 23 or 24. RSVP to
fdp_at_jcabot.com or doravec_at_iselabs.com