ELE22MIC Lecture 12

1
ELE22MIC Lecture 12 13

• Serial Communications
• Serial Data Formats - RS232
• 6850 ACIA
• HC-COMs Serial Port - 6551
• IBM PC UART The 16550 16554
• RS232 / ITU V.24 / EIA232
• Sample Interrupt Service Routine (ISR)

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Serial Data Transmission (1)

• Serial I/O is the transmission of data over a
  single communication line.
• Cheaper than parallel
• Data is moved sequentially one bit at a time.
• Requires a conversion from parallel data format
  to serial format.
• This conversion is normally performed by a shift
  register driven by a clock.

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Serial Data Transmission (2)

• At the receiving end, data must be reconstructed
  back into parallel format.
• Some method is required to identify bit
  boundaries.
• i.e. how do you differentiate between 000 and
  0000?

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Serial Data Transmission (3)

• Two methods
• Synchronous Transmission
• Use a common clock to synchronise the receiver
  with the transmitter.
• Therefore requires a separate tine to carry the
  clock.
• Asynchronous Transmission
• The receiver and transmitter has separate,
  independent, accurate local clocks.

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Synchronous Serial Data Transmission (4)

• Synchronous Transmission is used with the Serial
  Peripheral Interface (SPI)
• See lecture 11.
• Uses 4 wires
• Clock
• Data
• Select
• Ground

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Asynchronous Serial Data Transmission (1)

• RS232 Voltage Levels Data Format
• Line Transciever with Charge Pump -
• the MAX232 series.
• Serial Data Format
• Start Bit, Data Bits, Parity, Stop Bits
• Errors Framing, Overrun, False Start
• The 6850 ACIA (Asynchronous Communications
  Interface Adapter)
• AKA UART (Universal Asynchronous Receiver
  Transmitter) or ACE (Asynchronous Communications
  Element)
• The RS232 Transmission Distance Limits

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Clock Synchronisation (1)

• The receiver phase locks its local clock to the
  transmitter's clock by detecting the start bit
  and stop bits of a serial frame.
• Thus it does not require a separate clock line as
  the data line contains timing information.
• If the data is sampled in the mid-point of each
  bit the clock error less than to 5 can be
  tolerated with communication remaining error-free
  between transmitter and receiver.

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RS232 - Data Format
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Clock Synchronisation (2)

• Start bit signifies the beginning of the frame
• Stop bit(s) identify the end of the frame
• If the stop bits are received incorrectly it is
  assumed that the receivers clock has drifted out
  of phase, or some other error has occurred, and a
  FRAMING ERROR is declared

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Serial Data Bit Sampling

• The signal is sampled by the ACIA in the middle
  of each bit period.

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Serial Communication Speed

• The rate at which data is transmitted is called
  the bit-rate
• Bit-rate is measured in bits per second.
• Baud rate refers to the rate per second of the
  bit symbols used to transmit the serial data.
• i.e. it includes the synchronisation items
  start bit stop bit(s). For example If using 10
  bit symbols per 8 bit character at 9600 baud
  equates to a bit rate of 7680 data bits per
  second (or 960 Bytes per second).

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Serial Data Bit Error Detection

• In any data transfer there is the potential for
  bit-errors. Parity can be used as a check that
  the correct bit pattern is received.
• Parity calculation involves adding the 1 bits
  in a frame together.
• Even Parity
• Adding all bits in frame parity gt 0
• Odd Parity
• Adding all bits in frame parity gt 1

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Serial Data Bit Error Detection
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Bit Error Rate (BER) (1)

• The Bit Error Rate - Probability of bit error -
  is the number of bit errors measured at the
  receiver through a communication system. The
  transmission channel may be Radio, Optical Fibre,
  Copper Cable, etc.
• In analog communications the important unit of
  measure is the Signal to Noise ratio.
• These measures are useful to characterise a
  system and can be measured or simulated.

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Bit Error Rate (BER) (2)

• If the quality of the system is high, the single
  bit error rate may be measured in years. In this
  case a single parity bit would be sufficient to
  determine data errors re-transmission could
  recover the correct data.
• The probability of double-bit errors would become
  negligable. Double-bit errors cannot be detected
  using a single parity bit.

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Improving Noise Immunity

• One way of improving noise immunity sample
  multiple times through each bit and at each
  sample time, check the status of each bit. Take
  the most common value of the sample as the bit
  value.

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6850 Status Register
0 RDRF Receive Data Register Full 1 TDRE
Transmit Data Register Empty 2 DCD Data
Carrier Detect 3 CTS Clear To Send 4 FE
Framing Error 5 OVRN Receiver Overrun 6 PE
Parity Error 7 IRQ IRQ pending
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6850 Bus Interface
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6850 Control Register
Clock divisor 0 Counter Divisor Select 1 1
Counter Divisor Select 2 Communication
Settings 2 Word Select 1 3 Word Select 2 4
Word Select 3 Interrupt Control 5 Transmit
Control 1 6 Transmit Control 2 7 Receiver
Interrupt Enable
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6850 Configuration - Divisor
An ACIA may be configured to suit a range of
serial communications formats by setting the
appropriate bits in the control register Clock
divisor Control Register bits CR1, CR0 CR0
Counter Divisor Select 1 CR1 Counter Divisor
Select 2 CR1 CR0 Description 0 0 divide by
1 0 1 divide by 16 1 0 divide by 64 1 1
Master reset
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6850 Configuration - Word Format
Data word format Settings CR2 Word Select 1
CR3 Word Select 2 CR4 Word Select 3 CR4 CR3
CR2 Description 0 0 0 7 data bits, 2 stop bits,
even parity 0 0 1 7 data bits, 2 stop bits, odd
parity 0 1 0 7 data bits, 1 stop bit, even
parity 0 1 1 7 data bits, 1 stop bit, odd
parity 1 0 0 8 data bits, 2 stop bits, no
parity 1 0 1 8 data bits, 1 stop bit, no
parity 1 1 0 8 data bits, 1 stop bit, even
parity 1 1 1 8 data bits, 1 stop bit, odd parity
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6850 Configuration - Interrupts
Handshake and Interrupt Control CR5 Transmit
Control 1 CR6 Transmit Control 2 CR6
CR5 0 0 Set RTS 0, Inhibit Transmit
Interrupt 0 1 Set RTS 0, Enable Transmit
Interrupt 1 0 Set RTS 1, Inhibit Transmit
Interrupt 1 1 Set RTS 0, Transmit Break and
Inhibit Transmit Interrupt CR7 Receiver
Interrupt Enable CR7 0 - Disable Interrupt in
receive mode CR7 1 - Enable Interrupt in
receive mode
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HCCOMs RS232 interface
HCCOM uses Rockwell 6551 ACIA - similar to the
M6850. The MAX238 converts from 0-5 volt signals
to the /- 10V signals required for RS232
standard. - Charge Pump.
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Serial communications
16550 UART Configuration
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Serial communications
16550 UART Configuration At IO Address COM1
3F8..3FF, COM2 2F8..2FF, COM3 3E8..3EF, COM4
2F8..2FF
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(No Transcript)
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Serial communications
Interrupt Enable Register (IER) The IER enables
each of the five types of interrupts and enables
INTRPT in response to an interrupt generation.
The IER can also disable the interrupt system
by clearing bits 0 through 3. The contents of
this register are summarised in the previous table
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Serial communications
Interrupt Identification Register (IIR) P1 The
ACE has an on-chip interrupt generation and
prioritization capability. The ACE provides four
prioritized levels of interrupts Priority 1 -
Receiver line status (highest priority) Priority
2 - Receiver data ready/receiver character
time-out Priority 3 - Transmitter holding
register empty Priority 4 - Modem status (lowest
priority) When an interrupt is generated, the
IIR indicates that an interrupt is pending and
encodes the type of interrupt in its three least
significant bits (bits 0, 1, and 2).
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Serial communications
Interrupt Identification Register (IIR) P2 Detail
on each bit is as follows Bit 0 When bit 0 is
cleared, an interrupt is pending Bits 1 and 2
These two bits identify the highest priority
interrupt pending as indicated in the previous
table. Bit 3 This bit is always cleared in
16C450 mode. In FIFO mode, bit 3 is set with bit
2 to indicate that a time-out interrupt is
pending. Bits 4 and 5 not used (always
cleared). Bits 6 and 7 These bits are always
cleared in 16C450 mode. They are set when bit 0
of the FIFO control register is set.
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Serial communications
Line Control Register (LCR) In addition, the
programmer is able to retrieve, inspect, and
modify the contents of the LCR this
eliminates the need for separate storage of the
line characteristics in system memory. Bits 0
and 1 Number of bits in each serial
character. 005 bits, 016 bits, 107 bits,
118 bits Bit 2 Specifies either 1, 1.5 or 2
stop bits If Bit 3 parity bit is generated in
transmitted data between the last data word bit
and the first stop bit. In received data parity
is checked. If Bit 30 no parity is generated
or checked.
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Serial communications
Line Control Register (LCR) When parity is
enabled and Bit 41 Even Parity - An even number
of logic 1s in the data and parity bits is
selected. Bit40 odd parity - An odd number of
logic 1s is selected. Bit 51 Stick Parity. The
parity bit set to 0. Bit 50 Stick parity is
disabled.
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Serial communications
Line Control Register (LCR) Bit 6 Break control
bit. Bit 6 is set to force a break condition
i.e., a condition where SOUT is forced to the
spacing (cleared) state. Bit 7 Divisor Latch
Access Bit (DLAB). Bit 7 must be set to access
the divisor latches of the baud generator during
a read or write. Bit 7 must be cleared during a
read or write to access the receiver buffer, the
THR, or the IER.
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Serial communications
Line Status Register (LSR) Bit 0 Data Ready (DR)
indicator for the receiver. DR is set whenever a
complete incoming character has been received and
transferred into the RBR or the FIFO. DR is
cleared by reading all of the data in the RBR or
the FIFO. Bit 1 Overrun Error (OE) indicator.
When OE is set, it indicates that before the
character in the RBR was read, it was overwritten
by the next character transferred into the
register.
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Serial communications
Line Status Register (LSR) Bit 2 Parity Error
(PE) indicator. When PE is set, it indicates that
the parity of the received data character does
not match the parity selected. In the FIFO mode,
this error is associated with the particular
character in the FIFO to which it applies. This
error is revealed to the CPU when its associated
character is at the top of the FIFO. Bit 3
Framing Error (FE) indicator. When FE is set, it
indicates that the received character did not
have a valid (set) stop bit. Bit 4 Break
Interrupt (BI) indicator. When BI is set, it
indicates that the received data input was held
low for longer than a full-word transmission
time.
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Serial communications
Line Status Register (LSR) Bit 5 Transmit Hold
Register Empty (THRE) indicator. THRE is set when
the THR is empty, indicating that the ACE is
ready to transmit a new character. Bit 6
Transmitter Empty (TEMT) indicator. TEMT bit is
set when the THR and the TSR are both empty. When
either the THR or the TSR contains a data
character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and shift
register are both empty. Bit 7 Used In the FIFO
mode to indicate an error condition in the FIFO
buffer.
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Serial communications
Modem Control Register (MCR) Bit 0 This bit
(DTR) controls the DTR output. Bit 1 This bit
(RTS) controls the RTS output. Bit 2 This bit
(OUT1) controls OUT1, a user-designated output
signal. Bit 3 This bit (OUT2) controls OUT2, a
user-designated output signal. Bit 5 AutoFlow
Control Enable (AFE). When set, the autoflow
control is enabled.
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Serial communications
Modem Control Register (MCR) Bit 41 Local Loop
Back feature for diagnostic testing. The
transmitter SOUT is set high. The receiver SIN is
disconnected. The output of the TSR is looped
back into the receiver shift register input.
-The four modem control inputs (CTS, DSR, DCD,
and RI) are disconnected. The four modem
control outputs (DTR, RTS, OUT1, and OUT2) are
internally connected to the four modem control
inputs. The four modem control outputs are
forced to the inactive (high) levels.
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Serial communications
16550 UART BAUD RATE Generation using a
3.072-MHz Crystal
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Serial communications
16550 UART BAUD RATE Generation using a 1.8432
MHz Crystal
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Establishing A Comms Link
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Serial communications
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Serial communications
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Modern Serial communications
The 16C550x are functional upgrades of the of
the 16C450 - equivalent to the 16C450 on power
up, but can be placed in an alternate FIFO mode.
The automatic FIFO mode relieves the CPU of
excessive software overhead by buffering received
and transmitted characters. The receiver and
transmitter FIFOs store up to 16 bytes including
three additional bits of error status per byte
for the receiver FIFO.
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Modern Serial communications
In the FIFO mode, there is a selectable autoflow
control feature that can significantly reduce
software overload and increase system efficiency
by automatically controlling serial data flow
using RTS output and CTS input signals.
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Automatic Flow Control
ACE - Asynchronous Communications Element ACIA -
Asynchronous Communications Interface
Adapter UART - Universal Asyncronous Receiver
Transmitter
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RS232 Cables
DTE (Data Terminal Equipment eg Computers
Terminals) DTE Pin Descriptions
47
RS232 Cables
DCE to DTE Straight Through Computer to Modem
Cable
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RS232 Cables
Popular Wiring Methods for RS232 DTE to DTE
Null Modem - Eg Laplink
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RS232 Cables
DTE to DTE 3-Wire Null Modem Serial Terminal
to Computer Cable. Requires XON-XOFF flow control
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RS232 Cables
9 Pin to 25 Pin Connector DTE-DTE cable
51
Serial communications
Typical 3-wire serial connection
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Transmission Distance (1)

• RS232 Communications has limited slew rate to
  decrease EMI radiation.
• The slew rate is due to driver current limiting
  and capacitance between the wires.
• The longer the wire, the greater the capacitance.
  
• Cable with capacitance of 40pF/m gt 100m 4nF.

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Transmission Distance (2)
Speed versus distance limitations for
EIA/TIA-232. Data Rate (baud) Distance
(metres) 2400 65 4800 34 9600
16 19200 8 38400 4 57600
3 114200 1.5
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Interrupts (1)
There are two ways of telling when an I/O device
is ready 1. polling 2. interrupts An interrupt
is a way of diverting the processor's attention
away from its current program so that it may deal
with some event that has occurred. change in
state of a peripheral error from a
peripheral Using interrupts means the processor
does not have to continuously poll (check) the
status of I/O devices.
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Interrupts (2)
In some processors, an interrupt is also known as
a TRAP. In other cases TRAPs refer to
system-generated interrupts for example errors
such as division by 0, invalid opcode, access
invalid memory address There are two types of
interrupt hardware software A hardware
interrupt may be thought of as a
hardware-generated call to a special subroutine.
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Interrupts (3)
The 68HC11 has three direct hardware
interrupts. 1. IRQ saves the state of the
processor - loads the IRQ vector - executes the
IRQ ISR - restores the state of the processor -
orginal program in resumed. IRQ is maskable 2.
XIRQ high priority interrupt - non-maskable 3.
RESET - RESET line is held low for 8 cycles,
loads RESET vector, computer restarts and
previous CPU state is lost. RESET used on
power-up or after catastrophic hardware or
software failure non-maskable (highest priority).
Some processors have special interrupts known as
fast interrupts. (They are fast as they dont
save the cpu state, but leave that to the ISR
writers discretion)
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Interrupts (4)
When a processor receives an interrupt,
it completes its current instruction masks
further interrupts saves it current state loads
address of routine to handle interrupt executes
Interrupt Service Routine (ISR) to exit the
ISR Returns from interrupt using RTI
instruction which restores the previous state
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Interrupts (5)
Upon IRQ interrupt current instruction
completes, if interrupts are not masked the
interrupt mask is set, then the 68HC11 saves on
the stack program counter Y index register X
index register accumulator A accumulator
B CCR Upon returning from any interrupt - uses
the RTI instruction the 68HC11 pulls (pops) back
from the stack CCR accumulator B accumulator
A X index register Y index register program
counter
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Interrupts (6)
The Interrupt Service Routine (ISR) is a
subroutine specifically designed to handle a
given interrupt. An ISR is run when the
processor receives an interrupt. The CPU loads
the vector corresponding to that interrupt that
points to the appropriate ISR. Each interrupt
usually has a separate ISR associated with
it. An ISR will then - determine the source of
the interrupt - deal with event appropriately -
Return from Interrupt (execute an RTI instruction)
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Interrupts (7)
Interrupts may be handled in two ways Interrupt
polling - ISR checks each device to find the
device that generated the interrupt - used when
processor has limited number of interrupt lines
(wired-OR IRQ) - used when I/O device has
several sources of interrupt Vectored
interrupts - each device corresponds to a
single interrupt line and therefore a single
vector or - an I/O operation will supply the
processor with a vector appropriate for the event
that has occurred
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Vectored Interrupts (1)
Figure 3 Use of Priority Interrupt Controller
(PIC) to handle multiple interrupt sources M68000
with Intel 8259A PIC.
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Software Interrupts (1)
The 68HC11 has just one software interrupt
(swi). It is used to Call BUFFALO on HCCOM. On
80x86 systems the software interrupt is used by
programs to request services from the operating
system. ROM BIOS / DOS. eg Print this
character Read a character Read a string of
characters Read from the disk xxxx bytes to
memory yyyy Check for network errors Request
for termination How software interrupts are
implemented depends on the operating system.
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Software Interrupts (2)
Some computers may only have a few calls
supported. Other processors may hundreds of
different software interrupts and thousands of
operating system calls supported. When an
operating system is requested, via a Software
Interrupt, to perform a task for a program, it
has to have some way of determining which task is
needed. This is accomplished using handles. A
handle is a flag or indicator to the operating
system indicating what is wanted. Each service
available in the operating system has a handle
associated with it.
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Software Interrupts (3)
Read a character from the keyboard, and print a
character to the screen, and print a string of
characters to the screen. So we decide to assign
three handles 0 means Input a character from a
keyboard 1 means print a character to the
screen 2 means print a string of characters to
the screen Further decide that the handle will
be passed in the AccB. Hence, whenever an
operating system processes a software interrupt,
it checks the Acc. B and with the number found
there, it knows what service is required of the
calling program.
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Software Interrupts (4)
Along with handles, such things as where the
character to be printed is to be found where the
input character is to be stored, are also
defined. Let us suppose that we use the A
accumulator to hold the character in both of the
above instances. Then from application point of
view, to read a character from the keyboard and
then display it or screen, we have LDAB 0
load handle for reading a character SWI read
in character, returns with character in
accumulator A LDAB 1 load handle for
printing a character SWI print character
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Software Interrupts (5)
Now, if the B accumulator had an important value
which we wanted to keep, we would naturally push
it to the stack before we loaded the first
handle, then pull it back whet have finished.
So the above program becomes PSHB save
accumulator B to the stack LDAB 0 load
handler for reading a character SWI get
operating sys to read into AccA LDAB 1 load
handle for printing character SWI get
operating system to print char PULB pull
accumulator B from the stack
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Software Interrupts (6)
Why use software interrupts? Why use
handles? Operating systems and computers change
with each new release. Locations of I/O devices
and operating system subroutines may be different
in each new version. The only thing that is
constant is the location and function of the
vector table. The vectors in a computer will
always correctly locate the appropriate routines.
By requesting the operating system function via
a software interrupt, you avoid the possibility
of your code not working on a new machine or
operating system.
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Software Interrupts (7)
When processing an interrupt, the processor loads
the vector associated with that interrupt. The
vector is the start address of the Interrupt
Service Routine (ISR) for that interrupt. Vectors
are located at a predefined location in the
memory space. (Buffalo uses well-defined jump
table locations for access to I/O routines. SWI
is used to call Buffalo)
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Interrupt Vector Table
For the 68HC11, the main vectors are Address
Vector FFF2..FFF3 IRQ (external) FFF4..FFF5 XIRQ
(external) FFF6..FFF7 SWI (Software
Interrupt) FFF8..FFF9 Illegal opcode
trap FFFA..FFFB COP Failure FFFC..FFFD Clock
Monitor Fail FFFE..FFFF RESET The 68HC11 has
many other vectors, but these are less relevant
to this introductory course.
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Example simple ISR
LDX BUF_HEAD Get the buffer pointer LDAA 7000
load character from ACIA STAA 0, X store
character in buffer INX point to next byte
in buffer CPX BUF_END is (X gt end of
buffer), then BLO NO_WRAP circular buffer -
wrap to start LDX BUF_START NO_WRAP STX
BUF_HEAD save the pointer back RTI
return from interrupt BUF_HEAD RMB 2 BUF_START
EQU 7FF0 BUF_END EQU 7FFF
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ISR cycle timing
Instruction Completion 9 Interrupt Entry
14 LDX BUF_HEAD 3 LDAA 7000 2 STAA 0,
X 4 INX 1 CPX BUF_END
4 BLO NO_WRAP 3 LDX BUF_START
3 NO_WRAP STX BUF_HEAD 4 RTI 12 59
cycles (minimum) 0.5us ISR time 29us What
is this maximum data reception rate? 33898
interrupts / second, best case on 2MHz 68HC11 (8
MHz Crystal).
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Acknowledgements

• I used Altium Protel 98 and Protel DXP to create
  these schematic diagrams
• Motorola 11rm.pdf Reference Manual
• IEEE Electronics Engineers Handbook, 4th Edn,
  Donald Christiansen - Definitions of BAUD BER
• Seng Gohs original notes