ECE 353 Introduction to Microprocessor Systems

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ECE 353Introduction to Microprocessor Systems
Week 3

• Michael G. Morrow, P.E.

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Topics

• Code Generation and Debugging Tools
• ARM7TDMI Microprocessor
• Organization
• Programming

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Code Generation

• Programming Language Characteristics
• High-Level Language (HLL)
• Assembly Language
• Machine Language
• Assembler Functions
• What does an assembler do?
• Syntax checking
• Address and offset calculation
• Machine instruction encoding
• Macro and pseudo-instruction expansion

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Assembly Language

• Assembler Types
• Native assembler
• Cross-assembler
• General Instruction Syntax
• Label
• Mnemonic
• Operands
• Comments
• Key ARM Assembler Directives

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Code Generation Process Generic
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Code Generation Process ECE 353andECE 315
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Hardwarefor Sample Program
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Source Code File
Filename sample.s Author ECE 353
Staff Description sample program for week 3
lecture do NOT use this as the basis for
any programming! EXPORT Reset_Handler
make available to linker IOPORT_ADDRESS EQU
0x80001000 AREA Reset, CODE,
READONLY ARM Reset_Handler LDR
PC, aLoop jump absolute Loop
LDR R0, aPort load address of port
LDR R1, R0 read switch state
LSL R1, 8 shift left 8 bits
to align MVN R1, R1
complement STR R1, R0
write LEDs NOP do
nothing B Loop repeat
forever aLoop DCD Loop aPort DCD
IOPORT_ADDRESS END
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Assembler Listing File (1)
4 00000000 do NOT use this as
the basis for any programming! 5 00000000
6 00000000 EXPORT
Reset_Handler make available t
o
linker 7 00000000 8 00000000
80001000 IOPORT_ADDRESS
EQU
0x80001000 9 00000000 10 00000000
AREA Reset, CODE,
READONLY 11 00000000 ARM 12
00000000 13 00000000
Reset_Handler 14 00000000 E59FF018 LDR
PC, aLoop 15 00000004
Loop 16 00000004 E59F0018 LDR
R0, aPort load address of port 17
00000008 E5901000 LDR R1,
R0 read switch state 18 0000000C
E1A01401 LSL R1, 8
shift left 8 bits
to align 19
00000010 E1E01001 MVN R1, R1
complement 20 00000014 E5801000
STR R1, R0 write LEDs 21
00000018 E1A00000 NOP
do nothing 22 0000001C EAFFFFF8 B
Loop repeat forever 23
00000020 24 00000020 00000000
aLoop DCD Loop
25 00000024 80001000
aPort DCD IOPORT_ADDRESS 26
00000028 27 00000028
END
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Assembler Listing File (2)
Command Line --debug --xref --deviceDARMAD
--apcsinterwork -osample.o -IC\K eil\ARM\INC\ADI
--listsample.lst sample.s ARM Macro Assembler
Page 1 Alphabetic symbol ordering Relocatable
symbols Loop 00000004 Symbol Loop
Definitions At line 15 in file sample.s
Uses At line 22 in file sample.s At
line 24 in file sample.s Reset 00000000 Symbol
Reset Definitions At line 10 in file
sample.s Uses None Comment Reset
unused Reset_Handler 00000000 Symbol
Reset_Handler Definitions At line 13 in
file sample.s Uses At line 6 in file
sample.s Comment Reset_Handler used once
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Assembler Listing File (3)
Symbol aLoop Definitions At line 24 in
file sample.s Uses At line 14 in file
sample.s Comment aLoop used once aPort
00000024 Symbol aPort Definitions At
line 25 in file sample.s Uses At line 16
in file sample.s Comment aPort used once 5
symbols ARM Macro Assembler Page 1 Alphabetic
symbol ordering Absolute symbols IOPORT_ADDRESS
80001000 Symbol IOPORT_ADDRESS Definitions
At line 8 in file sample.s Uses At
line 25 in file sample.s Comment IOPORT_ADDRESS
used once 1 symbol 321 symbols in table
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Disassembly Window
0x00080000 E59FF018 DD
0xE59FF018 0x00080004 E59F0018 LDR
R0,PC,0x0018 0x00080008 E5901000 LDR
R1,R0 0x0008000C E1A01401 MOV R1,R1,LSL
8 0x00080010 E1E01001 MVN
R1,R1 0x00080014 E5801000 STR
R1,R0 0x00080018 E1A00000 NOP
0x0008001C EAFFFFF8 B
0x00080004 0x00080020 00080004 DD
0x00080004 0x00080024 80001000 ANDHI
R1,R0,R0 0x00080028 00000000 ANDEQ
R0,R0,R0 0x0008002C 00000000 ANDEQ
R0,R0,R0 0x00080030 00000000 ANDEQ
R0,R0,R0 0x00080034 00000000 ANDEQ R0,R0,R0
aLoop
aPort
B/BLltcondgt lttarget_addressgt RTL PC ? PC
(signed_immediate_24 ltlt 2)
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Linker Map File (1)
ARM Linker, RVCT3.0 Build 942 for uVision
Evaluation
Sectio
n Cross References

Image Symbol Table Local Symbols Symbol
Name Value Ov
Type Size Object(Section) sample.s
0x00000000 Number
0 sample.o ABSOLUTE Reset
0x00080000 Section
40 sample.o(Reset) Loop
0x00080004 ARM Code 0
sample.o(Reset) Global Symbols Symbol
Name Value Ov
Type Size Object(Section) BuildAttributes
THUMB_ISAv1ARM_ISAv4MPEAL22XL11S22IEEE1
IWUSESV6STKCKDUSESV7SHLOSPACEEBA8PRES8E
ABIv2 0x00000000 Number 0 anonobj.o
ABSOLUTE Reset_Handler
0x00080000 ARM Code 0
sample.o(Reset)
Me
mory Map of the image Image Entry point
0x00080000 Load Region LR_1 (Base 0x00080000,
Size 0x00000028, Max 0xffffffff, ABSOLUTE)
Execution Region ER_RO (Base 0x00080000, Size
0x00000028, Max 0xffffffff, ABSOLUTE) Base
Addr Size Type Attr Idx E
Section Name Object 0x00080000
0x00000028 Code RO 1 Reset
sample.o Execution Region ER_RW
(Base 0x00010000, Size 0x00000000, Max
0xffffffff, ABSOLUTE) No section
assigned to this execution region
Execution Region ER_ZI (Base 0x00010000, Size
0x00000000, Max 0xffffffff, ABSOLUTE)
No section assigned to this execution region
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Linker Map File (2)
Image component sizes Code (inc. data)
RO Data RW Data ZI Data Debug Object
Name 40 8 0 0
0 244 sample.o
--------------------------------------------------
---------------------- 40 8
0 0 0 244 Object
Totals 0 0 0
0 0 0 (incl. Generated)
0 0 0 0 0
0 (incl. Padding)
--------------------------------------------------
---------------------- 0 0
0 0 0 0 Library
Totals 0 0 0
0 0 0 (incl. Padding)
--------------------------------------------------
----------------------

Code (inc. data) RO Data RW
Data ZI Data Debug 40
8 0 0 0 244
Grand Totals 40 8 0
0 0 244 Image
Totals
Total
RO Size (Code RO Data) 40 (
0.04kB) Total RW Size (RW Data ZI Data)
0 ( 0.00kB) Total ROM Size
(Code RO Data RW Data) 40 (
0.04kB)

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Hex Record Format
0400000500080000EF 020000040008F2 1000000018F09
FE518009FE5001090E50114A0E1AD 100010000110E0E1001
080E50000A0E1F8FFFFEA38 0800200004000800001000803
C 00000001FF
0x00080000 E59FF018
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Debugger Basics

• So, why is it called debugging, anyway?
• Terminology
• Testing
• Debugging
• Types of errors
• Symbolic debugging
• UUT/DUT
• Typical Debugger Capabilities
• Display/modify machine state
• Load/run/halt
• Step-into / step-over
• Breakpoints

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Simulator

• Runs on a host computer, and simulates execution
  of your code. No actual hardware required.
• Strengths
• Useful for testing before hardware available,
  especially algorithm verification
• Can use file input to simulate external
  interfaces
• Weaknesses
• Slow host must execute many instructions for
  each simulated instruction usually not possible
  to get real-time performance
• Difficult to simulate complex processor
  environment and interactions need to have models

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Native Debugger

• Code is executed on a host computer with a
  compatible instruction set.
• Strengths
• Full speed execution
• Can use file input to simulate external
  interfaces
• Weaknesses
• Debugger and UUT share same resources best
  suited for non-I/O parts of code
• Most have a host computer with a compatible
  instruction set - not always available.

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Resident Monitor

• Monitor is a stand-alone program that runs on the
  UUT, typically communicates over serial interface
  to a terminal.
• Strengths
• Facilitates downloading and full-speed execution
  and debugging of code on actual hardware
• Weaknesses
• Usually have simple command set (i.e. LOAD, GO,
  etc.) and limited ability to display system state
• Monitor uses system resources, may alter
  performance of UUT software or require additional
  resources
• Program can crash monitor program

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Remote Debugger

• Similar to resident monitor, but only small
  debugger kernel on UUT. Main debugger software
  runs on a host computer connected to the UUT.
• Strengths
• Facilitates downloading and full-speed execution
  of code on actual hardware
• Usually support more advanced features (i.e.
  symbolic debugging, data visualization, etc.)
• Weaknesses
• Kernel uses (fewer) resources, may alter
  performance of UUT software or require additional
  resources
• Program can crash debug kernel

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In-Circuit Emulator (ICE)

• Replaces UUT CPU with hardware that gives full
  control of CPU pins (i.e. can run arbitrary bus
  cycles). Often contain overlay memory to allow
  testing of software before system hardware is
  available. May clamp over existing CPU that is
  soldered in place.
• Strengths
• Complete visibility and control of CPU activity
• Can set breakpoints on arbitrary bus operations
  (i.e. read X from Y)
• Record and playback execution traces
• Weaknesses
• Expensive!

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JTAG Emulators

• Special serial interface to the device (IEEE
  1149.1)
• Boundary scan cell
• Boundary scan chain
• Emulation (internal) scan chain
• Background debug support
• Strengths
• No extra hardware except for small connector
• Complete control over CPU state and operation
• Can use for production and field
  testing/debugging
• Weaknesses
• Relatively slow must load/retrieve CPU serially
• Actually stops CPU when loading/retrieving

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Hardware-Assisted Debug

• In microprocessors with on-chip nonvolatile
  memory (like the ADuC7026), it is not feasible to
  set software breakpoints
• Debug hardware is added to support debugging in
  these conditions
• Code breakpoint registers
• Data breakpoint registers
• ARM7 combines both of these into a watchpoint
  register set

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Code Development Tips

• Use structured programming methods
• No spaghetti code!
• Use descriptive symbols and names
• Write comments as you go (or before!)
• When fixing assembler errors, fix only the top
  one or two and re-assemble a lot of the later
  errors may be due to the first few
• When debugging, verify what the registers are
  loaded with as compared to what you think (know?)
  they should be loaded with
• Textbook has a good section on debugging

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ARM7TDMIProcessor Core
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ARM7 Operating Modes

• User
• Normal program execution mode
• System
• For running operating system tasks at user
  privilege level
• Supervisor
• Protected mode for operating system
• Abort
• Used to implement process and/or memory
  protection
• Two classes of aborts data abort, prefetch
  abort
• Undefined
• Supports software emulation of unsupported
  instructions and unimplemented hardware
  coprocessors
• FIQ
• Fast interrupt handling
• IRQ
• General purpose interrupt handling

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ARM7 Programmers Model

• R15-R0
• Sixteen general-purpose registers
• Special functions
• R15 is the Program Counter (PC)
• If R15 is the destination operand, some
  instructions will exhibit special behavior for
  mode changes
• R14 is the Link Register (LR)
• For subroutine calls and interrupts/exceptions,
  the return address is stored in LR. It must be
  saved before calls are made in the subroutine.
• R13 is used as the Stack Pointer (SP)

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ARM7 Programmers Model (cont)

• Current Process Status Register (CPSR)
• Condition code flags (N, Z, C, V)
• Interrupt disable bits (I, F)
• Thumb mode enable (T)
• Never change directly!
• Operating mode select
• Reserved bits
• Do not alter the state of these bits for
  compatibility with future ARM products
• I, F and mode cannot be changed in user mode!

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ARM7 Programmers Model (cont)

• Suspended Process Status Register (SPSR)
• SPSR is only present when the CPU is operating in
  one of the exception modes
• Each exception mode has its own SPSR, since
  exception handlers may cause other exceptions.
• SPSR is a copy of the CPSR immediately before the
  exception mode was entered.
• When returning from the exception, the value in
  SPSR is used to restore the CPSR to the proper
  state for the process that was interrupted.

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ARM7 Register Banking
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ARM7 Reset

• CPSR
• Supervisor mode
• I F set (interrupts disabled)
• T cleared (ARM mode)
• PC is cleared to 0x00000000 and an instruction is
  fetched
• This is the bootstrap instruction
• All register values except PC and CPSR are
  indeterminate

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ARM7 Reserved Addresses
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ARM7 Coprocessors

• The ARM architecture is designed to support the
  addition of tightly-coupled hardware coprocessors
• System control processor (CP15)
• Floating-point coprocessor
• Special instructions are used to read/write
  coprocessor registers
• If the coprocessor is not implemented, an
  undefined instruction exception occurs,
  permitting software emulation of the coprocessor
  functions.
• The ADuC7026 does not implement any coprocessors

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ARM7 Condition Codes
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ARM7 Condition Codes (cont)

• Things to remember when using conditions
• Signed and unsigned arithmetic require different
  conditions to get same result
• Unsigned HS equivalent to signed GE
• The AL (always) condition is implied if no
  condition mnemonic is used
• The meaning of the condition is true if op1 cond
  op2
• CMP R0, R1
• BLLT subroutine
• Subroutine called if R0 is less than R1 (signed)

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ARM7 Instruction Encoding
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Wrapping Up

• Homework 2 due Wednesday 9/30
• Reading for next week
• Chapter 4, 5
• ARMINSTREF
• Pre-Quiz 3 on Learn_at_UW, complete by Monday class
  time

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Boundary Scan I/O Cell
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Boundary Scan Chain
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Emulation Scan Chain
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RADM Grace Hopper

• References
• http//www.arlingtoncemetery.net/ghopper.htm
• http//www.history.navy.mil/photos/images/h96000/h
  96566kc.htm