Trigger interface module

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Trigger interface module

• Kjetil Ullaland, Sten Solli, Johan Alme

TPC Electronics meeting. CERN 13-14. Jan 2005
2
Overview

• Version 1.0
• Serial B channel
• Proposed new design (version 2.0)
• Status

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Previous design

• The complete design was hosted on the DCS FPGA.

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Version 1.0 Top level design
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Version 1.0 Block design
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Trigger info registers

• Trigger data is sorted and presented in such a
  way that it fits DAQ common data format.
• No extra load for the Data Assembler.

  From TTCrx internal counters
  From L2accept trigger message
  From L1 trigger message
  From Region of Interest message
  Unused bits buffered with zeros
Address 31   23   11 0
TriggerInfo1 8b 8b 8b 8b L1 Trigger Msg lt112gt L1 Trigger Msg lt112gt L1 Trigger Msg lt112gt L1 Trigger Msg lt112gt L1 Trigger Msg lt112gt 2b BCID lt110gt BCID lt110gt BCID lt110gt BCID lt110gt BCID lt110gt BCID lt110gt
TriggerInfo2 8b 8b 8b 8b OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt OrbitID lt230gt
TriggerInfo3 8b 8b 8b 8b L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt L2Detector lt230gt
TriggerInfo4 4b 4b 16b 16b 16b 16b 16b 16b 16b 16b TTCrx BunchCnt lt110gt TTCrx BunchCnt lt110gt TTCrx BunchCnt lt110gt TTCrx BunchCnt lt110gt TTCrx BunchCnt lt110gt TTCrx BunchCnt lt110gt
TriggerInfo5 L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt L2Class lt310gt
TriggerInfo6 RoI lt30gt RoI lt30gt 10b 10b 10b 10b 10b L2Class lt4932gt L2Class lt4932gt L2Class lt4932gt L2Class lt4932gt L2Class lt4932gt L2Class lt4932gt L2Class lt4932gt L2Class lt4932gt L2Class lt4932gt
TriggerInfo7 RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt RoI lt354gt
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Serial B channel

• Datastream on the serial B channel is enabled by
  setting bit 6 in the control register in TTCrx.
• New data on Serial B channel arrives straight
  after the TTCrx issues a L1accept.

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Serial B channel

• The data arrives in the following order
  (depending on type of trigger)
• L1 header
• CIT, RoC, ESR, L1SwC, L1Class
• L1 data
• L1Class
• L2a header
• BCID
• L2a data
• OrbitID, CiT, L2Sw, L2Cluster, L2Class
• L2r address
• BCID
• RoI header
• BCID
• RoI data
• RoIdata
• These data are stored in triggerinfo registers in
  the TTCrx receiver module.

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Version 2.0

• Split the trigger interface module in to two
  modules
• TTCrx controller module on the DCS board.
• TTCrx receiver module on the RCU board.
• This removes the DCS FPGA from the datapath.
• Datapath not reliable of parts that can fail
  because of SEFIs.
• Uses the Serial B channel for data
  transportation, instead of the data lines from
  the TTCrx.
• The data is transmitted using a 40 MHz clock
• Event counter numbers are generated by the TTCrx
  receiver module.
• TTCrx receiver module contains the triggerinfo
  registers.

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Version 2.0 - Top level
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Version 2.0 Block design
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TTCrx receiver module main tasks

• Handle L1 trigger
• Pass through and count
• Receive and decode messages over serial B channel
  and generate L2a trigger.
• Handle bad triggers
• Book keeping (counters )

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TTCrx controller module main tasks

• Initialization
• Control the TTCrx over the I2C bus.
• Status of the TTCrx.

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Status

• Recently started working on this module.
• The new design is based on Sten Sollis design.
• Specifications soon finished.