Compton Trigger Design Update

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Compton Trigger Design Update
Tanja Horn
Compton Working Group 6 June 2008
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CAEN Module V1495

• Commercially available
• General purpose VME board
• Can be directly customized by the user
• Field Programmable Gate Arrays (FPGA)

• 96 inputs with 32 outputs

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Background

• Fall 2007 Hall B IC trigger design (B. Raydo,
  S. Boyarinov)
• Jan-March 2008 Compton working group meeting.
  Trigger concept for Compton DAQ based on the
  existing Hall B design proposed (TH)
• March-May 2008 Development and implementation
  of Hall B trigger using similar technology (V.
  Kubarovsky et al.)
• June 2008 development of firmware for Compton
  DAQ could begin

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Design Criteria

• Four detector planes, 96 microstrips/plane
• Expected rate is 100 kHz on average
• Form trigger within 500ns
• Trigger efficiency is not critical
• Background suppression important

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Design Concept

• Design based on
• Modern hardware
• Existing software and firmware
• Cluster finding algorithm being developed by S.
  Boyarinov
• Flexibility of the design lies in the
  upgradability of the firmware
• Functionality can be added without additional
  hardware
• Incremental development possible

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Proposed Compton Trigger Layout
Discriminator, 16 chan
Discriminator, 16 chan
Discriminator, 16 chan
?
Master Trigger Board
Both stages of the trigger (plane and master)
require different firmware
Discriminator, 16 chan
Plane Trigger Boards
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Design Implementation

• Stage 1 Testing and Initial Operations
• Plane firmware OR of all strips
• Master firmware any logic through 41 lookup
  table (81 implemented)
• Stage 2 Regular Operations
• Plane firmware linear cluster finding, multi
  cluster rejection
• Master firmware cluster readout through master
  (input through ECL)?, 81 lookup table (trigger,
  veto), digital oscilloscope
• Additional features Graphical User Interface
  based on Hall B design
• Stage 3 Future Development
• Plane firmware
• Master firmware background suppression through
  simple tracking?

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ModelSIM-Altera
Code example from Ben

• Simulation needed to validate the design

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Rate Test (6/5/08) D16 CPU single cycle/DMA
single cycle
Transaction time 1.2 µs Readout rate 2 Mb/s
Figure from Ben
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Rate Test (6/5/08) D16 CPU block transfer/DMA
single cycle
Transaction time 0.43 µs Readout rate 4.7 Mb/s
Figure from Ben