Testing Solutions for Very Deep Sub-Micron CMOS Technologies

1
Testing Solutions for Very Deep Sub-Micron CMOS
Technologies
University of Ioannina Dept. of Computer
Science Ioannina - Greece
University of Athens Dept. of Informatics
Telecommunications Athens - Greece
University of Patras Dept. of Computer
Engineering Informatics Rio - Patras - Greece
Southern Illinois University Dept. of Electrical
Computer Engineering Carbondale - USA
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Delay TestingOn-Line and Off-Line DFT
Techniques

• A Zero Aliasing Built-In Self Test Technique for
  Delay Fault Testing DFT 1999

• A Versatile Built-In Self Test Scheme for Delay
  Fault Testing DATE 2000

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DFT for Delay Fault Testing
Transition Detection Circuitry
DFT-99
E
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Off-Line Delay Testing
DFT-99
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On-Line Delay Testing
DFT-99
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A Current Mode Technique for Delay Testing
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Off-Line Delay Testing
Test Phase
?1
?2
?3
?4
Valid Response
Erroneous Response
Erroneous Response
G-CLK
dmax
ENB
End of Valid Data Output Responses Enable TDU
Start of Current Test Phase Application of
Vj Enable TDU
End of Current Test Phase Start of Next Test
Phase Application of Vj1
Start of Valid Data Output Responses Disable TDU
DATE - 00
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On-Line Delay Testing
Detection Phase j
Detection Phase j1
Detection Phase j-1
?1
?2
?3
?4
Valid Response
Erroneous Response
Erroneous Response
CLK
ENB
Start of Detection Phase Input Ij Enable TDU
End of Valid Data Output Responses Start of
Detection Phase Input Ij1 Enable TDU
Start of Valid Data Output Responses Disable TDU
Start of Valid Data Output Responses Disable TDU
DATE - 00
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Concurrent TestingSoft and Timing Error
Detection Circuits and Techniques

• A Hierarchical Architecture for Concurrent Soft
  Error Detection Based on Current Sensing IOLTW
  2002

• A Sense Amplifier Based Circuit for Concurrent
  Detection of Soft and Timing Errors in CMOS ICs
  IOLTS 2003

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The Time Redundancy Technique
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Current Mode Comparator
Current Mode Comparator
DTCT
IOLTW - 02
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The Hierarchical Error Detection Architecture
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Multiple Lines Current Sensing Comparator
Multiple Lines Current Sensing Comparator ML-CSC
OUT
FFO
VDD
From the rest ACs of the cluster
ENB
Preset
From the rest CMs
ERR
EIF
N
SN
BICS
CSC_out
Activation Circuit (AC)
ENB
Current Mirror (CM)
IOLTW - 02
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Sense Amplifier Based Detector
IOLTS - 03
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Timing Waveforms
IOLTS - 03
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Detection Time vs Monitored Pairs
IOLTS - 03
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IDDQ TestingThe Challenge of VDSM Technologies

• Extending the Viability of IDDQ Testing in the
  Deep Submicron Era ISQED 2002

• An Embedded IDDQ Testing Architecture and
  Technique ISQED 2003

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Background Current Compensation
Vdd
CUT
Vdd
Leakage
IB
IDEF
Fault Indication Output
Compensator
BICS
T_EN
EN
BCC
Gnd
Gnd
Higher Current Resolution ITH as low as BICS
and/or BCC permit
ISQED - 02
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The BCC Based IDDQ Testing Technique
IBL ?R IBR
IBR
Current Mirror
Amplifier R to L
MIR_R_to_L
BCC
MIR_L_to_R
Current Mirror
Amplifier L to R
IBL
IBR ?L IBL
ISQED - 02
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Power Supply Distribution
CUT
V_GndR
V_GndL
BCC BICSs
T_EN
T_EN
sub-CUTL
sub-CUTR
Gnd
ISQED - 02
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Multiple Current Sink BCC Implementation
Background Current from sub-CUTR
Background Current from sub-CUTL
MIR_L_to_R
IBR
?L2 IBL
SEL1
SEL2
IBL
SELn
To the BICSR
T_EN
Current Mirror Amplifier
W1/L
Wn/L
W2/L
ISQED - 02
Gnd
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Embedded IDDQ Testing
ISQED - 03
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IEEE 1149.1 Based IDDQ Testing Architecture
ISQED - 03
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IDDQ Testing Flow Diagram
ISQED - 03
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Power Supply Distribution
ISQED - 03
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Memory TestingThe Neighborhood Pattern
Sensitive Fault Model

• A Test Pattern Generation Unit for Memory NPSF
  Built-In Self Test ICECS 2000

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A Deterministic TPG Unit
ICECS - 00
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FPGA Implementation
ICECS - 00