130nm Digital Sampler chip New results

1
130nm Digital Sampler chipNew results
Jean-François Genat

• on behalf of D. Fougeron, 1 R. Hermel 1, H.
  Lebbolo 2, T.H. Pham 2, R. Sefri, 2
• and
• A. Savoy-Navarro 2 1 LAPP Annecy, 2 LPNHE
  Paris
• 5th SiLC Meeting, April 25-27th 2007,
  Prague

2
Outline

• Goals
• Last results
• New results
• Further tests
• Next chip

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
3
Goals

• This chip
• Full readout chain integration in a single
  chip yes
• - Preamp-shaper yes
• - Trigger decision (analog sums) yes
• - Pulse Sampling Analog
  pipe-lines yes
• - On-chip digitization ADC yes
• - Buffering and pre-processing no
• Centroids, Least square fits,
• - Lossless compression and error codes
  no
• - Calibration and calibration
  management no
• - Power switching (ILC timing) no
• CMOS 130nm
  2006 yes
• CMOS 90nm 2007 no
• 512-1024 channels envisaged 4 channels

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
4
Front-end in 130nm

• 130nm CMOS
• Smaller
• Faster
• More radiation tolerant
• Lower power
• Will be (is) dominant in industry
• Drawbacks
• - Reduced voltage swing (Electric field
  constant)
• - Leaks (gate/subthreshold channel)
• - Models more complex, not always up to date
• - Crosstalk (digital-analog)

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
5
2006 Chips Summary
130nm Chip 1 (4 channels) -
Preamp-shapers Sparsifier - Pipeline
1 - ADC - Digital Chip 2 (One channel) -
Preamp-shapers Sparsifier - DC
servo - Pipeline 2 - DAC - Test structures
MOSFETS, passive
Under tests
J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
6
4-channel chip
Channel n1
Sparsifier
Can be used for a trigger
S aiVi gt th
Time tag
Wilkinson ADC
Channel n-1
reset
reset
Analog samplers, (slow)
Strip
Ch
Preamp Shapers
Waveforms
Counter
UMC CMOS 130nm
Clock 3-96 MHz
J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
7
Targeted

• Amplifier 20 mV/MIP gain
• Shaper
• Sparsifier threshold on analog sum
• Sampler 16-deep
• ADC 10-bit
• Noise
• Measured with 180nm CMOS
• 375 10.5 e-/pF _at_ 3 ms shaping,
  90mW power

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
8
Outline

• 130 nm chip goals
• February results
• Present results
• Further tests
• Next chip

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
9
Silicon
180nm 130nm
Picture
J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
10
130nm chip noise results (2/07)
Gain OK 30 mV/MIP OK Dynamics
30 MIPs _at_ 5 OK Peaking time .8 2ms
.7 - 3 ms
Power (Preamp Shaper) 290 mW
Noise 130nm _at_ 0.8 ms 850 14 e-/pF
130nm _at_ 2 ms 625 9
e-/pF 625sqrt(2/3 ms)510 e-/pF 180nm _at_
3 ms 375 10.5 e-/pF
J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
11
Outline

• 130 nm chip goals
• Last results
• Present results
• Further tests
• Next chip

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
12
Analog pipeline output
Simulation of the analog pipeline
Measured output of the ADC
J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
13
ADC
J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
14
Sampler ADC
Waveform biased by the output pad parasitic
capacitance ( 1pF) Chip130-2 under tests
buffer between sampler and ADC
J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
15
Outline

• 130 nm chip goals
• Last results
• Present results
• Further tests
• Next chip

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
16
130-1 next tests

• Measure ADC extensively
• Linearities
• integral, differential
• Noise
• fixed pattern, random
• Speed
• maximum clock rate
• Effective number of bits (ENOB)

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
17
130nm Chip 2
DC Servo
Sparsifier S ai Vi gt th
Channel n-1
ADC
Channel n1
ramp
Analog Pipe-line
Preamp and Shapers
J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
18
130-2 tests (LAPP Annecy)

• Measure improved pipeline extensively
• Denis Fougerons (LAPP) design
• Linearities
• integral, differential
• Noise
• fixed pattern, random
• Speed
• maximum clock rate
• Droop
• Hold data for 1ms at ILC

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
19
Outline

• 130 nm chip goals
• Last results
• Present results
• Further tests
• Next chip

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
20
Next chip

• Equip a detector
• Lab test bench and 2007 beam-tests
• 130nm chips 1 2 128 channels
• - Preamp-shapers sparsifier
• - Pipeline
• - ADC
• - Digital
• - Calibration
• - Power cycling

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
21
Power cycling
Switch the current sources between zero and a
small fraction (10-2 to 10-3 )

SLEEP signal
C
This option switches the current source feeding
both the preamplifier shaper between 2 values
to be determined by
simulation. Zero or a small fraction (0.1 -
1) of biasing current is held during
 power off .
Zero-power option tested on 180nm chip with 2 ms
recover time constant
J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
22
Planned Digital Front-End

• Chip control
• Buffer memory
• Processing for
• - Calibrations
• - Amplitude and time least squares estimation,
  centroids
• - Raw data lossless compression
• Tools
• - Digital libraries in 130nm CMOS available
• - Synthesis from VHDL/Verilog
• - SRAM
• - Some IPs PLLs
• - Need for a mixed-mode simulator

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
23
Some issues with 130nm design

• Noise likely not model pessimistic, but
  measured acceptable
• Design rules more constraining
• Some (via densities) not available under
  Cadence
• Calibre (Mentor) required
• Lower power supplies voltages
• Low Vt transistors leaky (Low leakage
  option available)

J-F Genat, 5th SiLC meeting, Prague, April
25-27th 2007
24
The End
25
Backup
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
26
Possible issues noise 130nm vs 180nm
(simulation)

• PMOS

180nm gm944.4uS,gms203.1uS1MHz ?
3.508nV/sqrt(Hz)Thermal noise hand calculation
3.42nV/sqrt(Hz)
130nm W/L 2mm/0.5uIds 38.79u,Vgs-190mV,Vds-
600mVgm815.245u,gms354.118u1MHz ?
7.16nV/sqrt(Hz)Thermal noise hand calculation
3.68nV/sqrt(Hz)
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
27
Noise 130nm vs 180nm(simulation)

• NMOS

130nm W/L 50u/0.5uIds48.0505u,Vgs260mV,Vds1.
2Vgm772.031uS,gms245.341uS,gds6.3575uS1MHz
--gt 24.65nV/sqrt(Hz)100MHz --gt
5nV/sqrt(Hz)Thermal noise hand calculation
3.78nV/sqrt(Hz)
180nm W/L50u/0.5uIds47uA,Vgs300mV,Vds1.2Vgm
842.8uS,gms141.2uS,gds16.05uS1MHz --gt
4nV/sqrt(Hz)10MHz --gt 3.49nV/sqrt(Hz)Thermal
noise hand calculation 3.62nV/sqrt(Hz)
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
28
Follower
Preamp CR RC Shaper
Comparator
29
130-90nm noise evaluation (STM process)
L. Ratti et al FE2006 Perugia
1 MHz
100 mA
1mA
J-F Genat 4th SiLC Workshop Dec
18th 20th 2006 Barcelone
30
Noise origin

• Thermal noise white 4 kT/gm
• Excess noise not so white due to
  process features (?)
• 1/f noise due to
• - Traps at the gate dielectrics interfaces
• - Mobility fluctuations in the channel
• UMC models and measurements
• The gate dielectric in 130nm induces more
  traps compared to 180nm
• degrading 1/f noise. No more SiO2 in 90nm next
  generation CMOS
• -gt hi-k dielectrics (Hf, Zr )
• - Some thermal excess noise shows up
• Ratti et al. (Pavia, Bergamo), CERN
• - Both ST90nm and IBM 130nm show better 1/f
  noise performance
• To be looked at UMC 90nm simulations

J-F Genat 4th SiLC Workshop Dec
18th 20th 2006 Barcelone
31
Backup
32
Silicon strips readout using CMOS Deep Sub-Micron
Technologies

• Jean-Francois Genat
• Leuven, Feb 26th 2007
• 2 J. David, 2 M. Dellhot, D. Fougeron, 1 R.
  Hermel 1,
• H. Lebbolo2 , T.H. Pham 2, F. Rossel 2, A.
  Savoy-Navarro 2,
• R. Sefri 2 , S. Vilalte 1 1 LAPP Annecy, 2
  LPNHE Paris
• Help from IMEC-Leuven (Europractice)
• C. Das, E. Deumens, P Malisse

33
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

34
Silicon strips parameters

• 4-5 106 Silicon strips
• 10 - 60 cm long
• Thickness Inner 150 -200mm
• Outer -400mm
• Strip pitch 50 mm
• Inner Double sided AC coupled
• Outer Single sided DC coupled

35
Silicon strips data at the ILC

• Pulse height Cluster centroid to get a few
  µm position resolution
• Detector pulse analog sampling to get
  accurate charge
• estimation
• Time Two scales
• Coarse 150-300 ns for BC identification,
  80ns sampling
• Shaping time of the order of the
  microsecond
• Fine nanosecond timing for the
  coordinate along the strip
• 10ns sampling
• Not to replace another layer or double
  sided
• Position estimation to a few cm using
  pulse reconstruction from samples
• Shaping time 20-50 ns

36
Coordinate along the strip
SPICE
L 28nH R 5 W
Ci500 fF
15 ns
90cm
V 6 107 m/s c/5
Cs 100 fF
1 ns time resolution is 6 cm

37
Measured Pulse Velocity
Measured velocity 5.5cm/ns Measured moving a
laser diode along 24 cm
38
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

39
Technologies

• Silicon detector and VLSI technologies allow to
  improve detector and front-end electronics
  integration
• Front-end chips
• Thinner CMOS processes 250, 180, 130, 90 nm
  
• now available from UMC, TSMC
• SiGe, less 1/f noise, faster
• Chip thinning down to 50 mm ?
• More channels on a chip, more functionalities,
  less power
• Connectivity
• 3D ? On detector bump-bonding ? Stud bonding ?
• Stud bonding sufficient if pitch more than 50mm
• Smaller pitch detectors, better position and time
  resolution.

40
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

41
Integrated functionalities

• Full readout chain integration in a single chip
• - Preamp-shaper
• - Trigger decision (analog sums)
  compact data
• - Sampling Analog pipe-lines
• - On-chip digitization
• - Buffering
• - Digital Processing Centroids and Least
  Squares time/amplitude estimation
• - Calibration and calibration management
• - Power switching
• Presently 128 channels (APV, SVX) chips, 256-1024
  envisaged

42
Front-End Chip

• Integrate 512-1024 channels in 90nm CMOS
• Charge Amplifiers 20-30 mV/MIP over 30 MIP
• Shapers - slow 500 ns 1 ms
• - fast 20-50 ns
• Zero-suppression threshold the sum of
  adjacent channels
• 2D analog memory - 8-16 samples
• 80 ns and 10 ns sampling clocks
• - Event buffer 16-deep
• ADC 10 bits
• Buffering
• Calibration
• Power switching saves a factor 100-200

• ILC timing 1 ms 3-6000 trains
  _at_150-300ns / BC
• 200ms in between

43
Foreseen Front-end architecture
trigger
Channel n1
Sparsifier
S aiVi gt th
Wilkinson ADC
Calibration Control
Time tag
reset
Channel n-1
reset
Analog samplers, slow, fast
Strip
Ch
Storage
Waveforms
Counter
Preamp Shapers
Charge 1-40 MIP, Time resolution BC tagging
150-300ns, fine 1ns
Technologies Deep Sub-Micron CMOS 180-130nm
Future SiGe /or deeper DSM
44
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
45
Silicon 2005
- Preamp - Shaper - Sample Hold - Comparator
3mm
16 1 channel UMC 180nm chip (layout and
picture)
46
Process spreads
Process spreads 3.3 (same wafer)
Preamp gains statistics (same wafer)
47
Shaper output noise
375 e- RMS
375 e- 10.4 e-/pF input noise with chip-on-board
wiring 275 8.9/pFsimulated
48
Linearities 180nm chip
/-1.5 /-0.5 expected
/-6 /-1.5 expected
49
Tests conclusions on UMC 180 nm chips
12 chips tested (end 2005) The UMC CMOS
180nm process is mature and reliable -
Models mainly OK - Only
one transistor failure over 12 chips -
Process spreads of a few 90Sr Source tests
with 180nm chip connected to a Si detector and
compared with VA1 chip from Ideas (see test
bench section) S/N 10 still system
noise dominating
50
Outline

• Detector data
• Technologies
• Front-End Electronics
• 180nm chip
• 130nm chips
• Future plans

51
Front-end in CMOS 130nm 2006-2007

• 130nm CMOS motivations
• Benefits
• Smaller
• Faster
• - More radiation tolerant
• - Less power
• - Presently dominant in the IC industry
• Issues
• - Design more constraining (Design rules)
• - Reduced voltage swing (Electric field
  constant)
• - Leaks
  (gate/subthreshold channel)
• - Models more complex, sometimes still not
  accurate

52
UMC Technology parameters

• 180 nm 130nm
• 3.3V transistors yes
  yes
• Logic supply 1.8V
  1.2V
• Metals layers 6 Al
  8 Cu
• MIM capacitors 1fF/mm² 1.5
  fF/mm2
• Transistors Three Vt options Low
  leakage option

Useful for analog storage during lt 1 ms
53
130nm 4-channel test chip
Channel n1
Zero-suppression
Can be used for a trigger
S aiVi gt th
Time tag
Ramp ADC
Channel n-1
reset
reset
Analog samplers, (slow)
Strip
Ch
Preamp Shaper DC servo implemented for DC
coupled detectors
Waveforms
Counter
UMC CMOS 130nm
Received in 2006 Being tested Analog OK,
Digital under tests
Clock 3-96 MHz
54
Analog pipeline simulation
55
Silicon
180nm 130nm
Picture
56
Noise130nm vs 180nm (simulation)

• PMOS

180nm gm944.4uS Id 30 uA Weak
inversion1MHz ? 3.508nV/sqrt(Hz) Thermal noise
hand calculation 3.42nV/sqrt(Hz)
130nm gm815.245uSId 60 uA Moderate
inversion 1MHz ? 7.16nV/sqrt(Hz) Thermal noise
hand calculation 3.68nV/sqrt(Hz)
Measurements on 130nm show 2 x better results !
57
130nm-1 design

• Noise models pessimistic ? 130nm CMOS Silicon
  actually 2x better !
• Design rules more constraining
• Post layout simulations at Leuven (Mentor)
• Some design rules (via densities) not
  available under Cadence
• Calibre (Mentor) required

58
130nm-1 conclusions

• Good matching wrt simulation
• Except noise which is
• much better !
• - Still lot to test pipe-line and digital
• Statistics available from two wafers (70
  chips)
• Very encouraging results

Go to 90 nm ?
59
130nm-2 design

• One channel version with
• Servo DC
• Improved pipe-line
• Calibration DAC

Layout Picture One
channel 1.5 x 1.5 mm2
60
130nm-2 architecture
DC servo to accommodate DC coupled detectors,
DAC calibration, Improved pipe-line
Preamp Shaper
Analog sampler
DC reference
Received January 5th 2007 Test card under
wiring Test stand under work
61
Planned on-chip digital

• Chip control
• Buffer memory
• Processing for
• - Calibrations
• - Amplitude and time least squares estimation,
  centroids
• Tools
• - Digital libraries in 130nm CMOS available
  (VST)
• - Place Route tools Cadence design kits
  
• from Europractice (Leuven, Belgium)
• Mixed mode needed
• - Synthesis from VHDL/Verilog
• - Some IPs PLLs, SRAM

62
Wiring Detector to FE Chips
Wire bonding Flip Chip
Technology
Courtesy Marty Breidenbach (Cal SiD)
OR (later)
63
Wiring Detector to FE Chips
Courtesy Ray Yarema, FEE 2006, Perugia
64
3D Wiring
Courtesy Ray Yarema, FEE 2006, Perugia
65
Manuel Lozano (CNM Barcelona)Chip connection

• Wire bonding
• Only periphery of chip available for IO
• connections
• Mechanical bonding of one pin at a time
• (sequential)
• Cooling from back of chip
• High inductance (1nH)
• Mechanical breakage risk (i.e. CMS, CDF)
• Flip-chip
• Whole chip area available for IO connections
• Automatic alignment
• One step process (parallel)
• Cooling via balls (front) and back if required
• Thermal matching between chip and substrate
• required
• Low inductance (0.1nH)

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
66
Manuel Lozano (CNM Barcelona)Bump bonding
flip chip technology

• Electrical connection of chip to
• substrate or chip to chip face to face
• flip chip
• Use of small metal bumps
• bump bonding

CNM

• Process steps
• Pad metal conditioning
• Under Bump Metallisation (UBM)
• Bump growing in one or two of the
• elements
• Flip chip and alignment
• Reflow
• Optionally underfilling

67
Manuel Lozano (CNM Barcelona)Bump bonding
flip chip technology

• Bumping technologies
• Evaporation through metallic
• mask
• Evaporation with thick
• photoresist
• Screen printing
• Stud bumping (SBB)
• Electroplating
• Electroless plating
• Conductive Polymer Bumps
• Indium evaporation

• Expensive technology
• Especially for small quantities
• (as in HEP)
• Big overhead of NRE costs
• Minimal pitch reported 18 µm but ...
• Few commercial companies for fine
• pitch applications (lt 75 µm)

68
The End
69
The SiTR-130_1 chip
180nm 130nm
Picture
70
Possible issues noise 130nm vs 180nm
(simulation)

• PMOS

180nm gm944.4uS1MHz ? 3.508nV/sqrt(Hz) Thermal
noise hand calculation 3.42nV/sqrt(Hz)
130nm gm815.245uS1MHz ? 7.16nV/sqrt(Hz) Therma
l noise hand calculation 3.68nV/sqrt(Hz)
Measurements show 2 times better results
71
SiTR-130_1 tests results
Gain OK 30 mV/MIP OK Dynamics 30
MIPs _at_ 5 OK Peaking time 0.8 2ms
0.7 - 3 ms
Power (Preamp Shaper) 300 mW
Noise comparative 130nm _at_ 0.8 ms 850
14e-/pF 130nm _at_ 2 ms
625 9e-/pF 180nm _at_ 3 ms 360 10.5
e-/pF
72
Some issues with 130nm design

• Noise models pessimistic, Silicon actually
  much better !
• Design rules more constraining
• Some design kits are not fully developed and
  thus
• additional effort needed

73
Power dissipation budget(measured)
Preamp Shaper Zero suppr. Pipe-line Total Analog ADC Logic Total Digital
180nm/ch 90 180 270

130nm/ch 148 148 198 10 575 66
Common 100 5 96 101
Final goal 1 mWatt/channel all included (looks
achievable)
74
Next developments

• Implement the fast (20-50ns shaping) version in
  Silicon-Germanium
• including
• - Preamp Shaper (20-100ns)
• Fast sampling
• Submit a full 128 channel version in 130nm CMOS
  including
• slow and fast analog processing, power cycling,
  digital

75
Planned on-chip digital

• Chip control
• Buffer memory
• Processing for
• - Calibrations
• - Amplitude and time least squares estimation,
  centroids
• Tools
• - Digital libraries in 130nm CMOS available
  (VST)
• - Place Route tools Cadence design kits
  
• from Europractice (Leuven, Belgium)
• - Synthesis from VHDL/Verilog
• - Some IPs PLLs, SRAM

76
Chip connection on µstrips

• Wire bonding
• Only periphery of chip available for IO
• connections
• Mechanical bonding of one pin at a time
• (sequential)
• Cooling from back of chip
• High inductance (1nH)
• Mechanical breakage risk
• Flip-chip
• Whole chip area available for IO connections
• Automatic alignment
• One step process (parallel)
• Cooling via balls (front) and back if required
• Thermal matching between chip and substrate
• required
• Low inductance (0.1nH)

77
Next developments

• Implement the fast (20-50ns shaping) version in
  Silicon-Germanium
• including
• - Preamp Shaper (20-100ns)
• Fast sampling
• Submit a full 128 channel version in 130nm CMOS
  including
• slow and fast analog processing, power cycling,
  digital

78
Planned on-chip digital

• Chip control
• Buffer memory
• Processing for
• - Calibrations
• - Amplitude and time least squares estimation,
  centroids
• Tools
• - Digital libraries in 130nm CMOS available
  (VST)
• - Place Route tools Cadence design kits
  
• from Europractice (Leuven, Belgium)
• - Synthesis from VHDL/Verilog
• - Some IPs PLLs, SRAM

79
Chip connection on µstrips

• Wire bonding
• Only periphery of chip available for IO
• connections
• Mechanical bonding of one pin at a time
• (sequential)
• Cooling from back of chip
• High inductance (1nH)
• Mechanical breakage risk
• Flip-chip
• Whole chip area available for IO connections
• Automatic alignment
• One step process (parallel)
• Cooling via balls (front) and back if required
• Thermal matching between chip and substrate
• required
• Low inductance (0.1nH)

80
1st step bump bonding FE on detectorStudying
flip-chip FEE chips on stripsIMB-CNM, VTT, HIP,
LPNHE, Liverpool (firms)

• Design of the fan-in fan-out on the µstrip sensor
• 1st case 128 ch
• 2nd case 1024 channel
• The design is starting
• have a foundry or a firm ready to implement
  it on the sensor
• Bump bonding of the FEE chip
• crucial issue here have a working chip
• with the required
  nb of channels
• (by end 2007)

81
2nd step cabling gt useTape Automated Bonding
(TAB)or????????Dont forget auxiliary
electronicsthat degrade any fancy solution on
paperex decoupling capacitors
82
A few words about cabling and connection to the
overall DAQ system preliminary thoughts

• A preparer

83
Chip connection on µstrips

• Wire bonding
• Only periphery of chip available for IO
• connections
• Mechanical bonding of one pin at a time
• (sequential)
• Cooling from back of chip
• High inductance (1nH)
• Mechanical breakage risk
• Flip-chip
• Whole chip area available for IO connections
• Automatic alignment
• One step process (parallel)
• Cooling via balls (front) and back if required
• Thermal matching between chip and substrate
• required
• Low inductance (0.1nH)

84
1st step bump bonding FE on detectorStudying
flip-chip FEE chips on stripsIMB-CNM, VTT, HIP,
LPNHE, Liverpool (firms)

• Design of the fan-in fan-out on the µstrip sensor
• 1st case 128 ch
• 2nd case 1024 channel
• The design is starting
• have a foundry or a firm ready to implement
  it on the sensor
• Bump bonding of the FEE chip
• crucial issue here have a working chip
• with the required
  nb of channels
• (by end 2007)

85
2nd step cabling gt useTape Automated Bonding
(TAB)or????????Dont forget auxiliary
electronicsthat degrade any fancy solution on
paperex decoupling capacitors
86
Next developments

• Implement the fast (20-50ns shaping) version in
  Silicon-Germanium
• including
• - Preamp Shaper (20-100ns)
• Fast sampling
• Submit a full 128 channel version in 130nm CMOS
  including
• slow and fast analog processing, power cycling,
  digital

87
Planned on-chip digital

• Chip control
• Buffer memory
• Processing for
• - Calibrations
• - Amplitude and time least squares estimation,
  centroids
• Tools
• - Digital libraries in 130nm CMOS available
  (VST)
• - Place Route tools Cadence design kits
  
• from Europractice (Leuven, Belgium)
• - Synthesis from VHDL/Verilog
• - Some IPs PLLs, SRAM

88
Chip connection on µstrips

• Wire bonding
• Only periphery of chip available for IO
• connections
• Mechanical bonding of one pin at a time
• (sequential)
• Cooling from back of chip
• High inductance (1nH)
• Mechanical breakage risk
• Flip-chip
• Whole chip area available for IO connections
• Automatic alignment
• One step process (parallel)
• Cooling via balls (front) and back if required
• Thermal matching between chip and substrate
• required
• Low inductance (0.1nH)

89
1st step bump bonding FE on detectorStudying
flip-chip FEE chips on stripsIMB-CNM, VTT, HIP,
LPNHE, Liverpool (firms)

• Design of the fan-in fan-out on the µstrip sensor
• 1st case 128 ch
• 2nd case 1024 channel
• The design is starting
• have a foundry or a firm ready to implement
  it on the sensor
• Bump bonding of the FEE chip
• crucial issue here have a working chip
• with the required
  nb of channels
• (by end 2007)

90
2nd step cabling gt useTape Automated Bonding
(TAB)or????????Dont forget auxiliary
electronicsthat degrade any fancy solution on
paperex decoupling capacitors
91
backup
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
92
Beam-tests at DESY
October 2006
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
93
Wiring Detector to FE Chips
Wire bonding Flip Chip
Technology
Courtesy Marty Breidenbach (Cal SiD)
OR (later)
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
94
Wiring Detector to FE Chips
Courtesy Ray Yarema, FEE 2006, Perugia
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
95
3D Wiring
Courtesy Ray Yarema, FEE 2006, Perugia
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
96
Manuel Lozano (CNM Barcelona)Chip connection

• Wire bonding
• Only periphery of chip available for IO
• connections
• Mechanical bonding of one pin at a time
• (sequential)
• Cooling from back of chip
• High inductance (1nH)
• Mechanical breakage risk (i.e. CMS, CDF)
• Flip-chip
• Whole chip area available for IO connections
• Automatic alignment
• One step process (parallel)
• Cooling via balls (front) and back if required
• Thermal matching between chip and substrate
• required
• Low inductance (0.1nH)

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
97
Manuel Lozano (CNM Barcelona)Bump bonding
flip chip technology

• Electrical connection of chip to
• substrate or chip to chip face to face
• flip chip
• Use of small metal bumps
• bump bonding

CNM

• Process steps
• Pad metal conditioning
• Under Bump Metallisation (UBM)
• Bump growing in one or two of the
• elements
• Flip chip and alignment
• Reflow
• Optionally underfilling

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
98
Manuel Lozano (CNM Barcelona)Bump bonding
flip chip technology

• Bumping technologies
• Evaporation through metallic
• mask
• Evaporation with thick
• photoresist
• Screen printing
• Stud bumping (SBB)
• Electroplating
• Electroless plating
• Conductive Polymer Bumps
• Indium evaporation

• Expensive technology
• Especially for small quantities
• (as in HEP)
• Big overhead of NRE costs
• Minimal pitch reported 18 µm but ...
• Few commercial companies for fine
• pitch applications (lt 75 µm)

J-F Genat, LECC06, Valencia, Sept 25-29th
2006
99
Noise 130nm vs 180nm(simulation)

• NMOS

130nm W/L 50u/0.5uIds48.0505u,Vgs260mV,Vds1.
2Vgm772.031uS,gms245.341uS,gds6.3575uS1MHz
--gt 24.65nV/sqrt(Hz)100MHz --gt
5nV/sqrt(Hz)Thermal noise hand calculation
3.78nV/sqrt(Hz)
180nm W/L50u/0.5uIds47uA,Vgs300mV,Vds1.2Vgm
842.8uS,gms141.2uS,gds16.05uS1MHz --gt
4nV/sqrt(Hz)10MHz --gt 3.49nV/sqrt(Hz)Thermal
noise hand calculation 3.62nV/sqrt(Hz)
J-F Genat, LECC06, Valencia, Sept 25-29th
2006
100
Noise 130nm vs 180nm (UMC)
Models

• 1/f NMOS 130/180 factor 6 worse

• Thermal 130/180 factor 1.4
  worse

130nm W/L 50/0.5 Ids48 uA gm770uS 1MHz
--gt 24 nV/sqrt(Hz)100MHz --gt
5nV/sqrt(Hz)Calculation 3.8nV/sqrt(Hz)
180nm W/L50/0.5 Ids47uA gm840uS1MHz --gt 4
nV/sqrt(Hz)10MHz --gt 3.5nV/sqrt(Hz)Calcualtio
n 3.6nV/sqrt(Hz)
Measurements give an overall factor of 1.5
between 130 and 180nm at 800 ns and 3ms shaping
time (look at 130nm at 2 ms)
J-F Genat 4th SiLC Workshop Dec
18th 20th 2006 Barcelone
101
Manuel Lozano (CNM Barcelona)Chip connection

• Wire bonding
• Only periphery of chip available for IO
• connections
• Mechanical bonding of one pin at a time
• (sequential)
• Cooling from back of chip
• High inductance (1nH)
• Mechanical breakage risk (i.e. CMS, CDF)
• Flip-chip
• Whole chip area available for IO connections
• Automatic alignment
• One step process (parallel)
• Cooling via balls (front) and back if required
• Thermal matching between chip and substrate
• required
• Low inductance (0.1nH)

102
Manuel Lozano (CNM Barcelona)Bump bonding
flip chip technology

• Electrical connection of chip to
• substrate or chip to chip face to face
• flip chip
• Use of small metal bumps
• bump bonding

CNM

• Process steps
• Pad metal conditioning
• Under Bump Metallisation (UBM)
• Bump growing in one or two of the
• elements
• Flip chip and alignment
• Reflow
• Optionally underfilling

103
Manuel Lozano (CNM Barcelona)Bump bonding
flip chip technology

• Bumping technologies
• Evaporation through metallic
• mask
• Evaporation with thick
• photoresist
• Screen printing
• Stud bumping (SBB)
• Electroplating
• Electroless plating
• Conductive Polymer Bumps
• Indium evaporation

• Expensive technology
• Especially for small quantities
• (as in HEP)
• Big overhead of NRE costs
• Minimal pitch reported 18 µm but ...
• Few commercial companies for fine
• pitch applications (lt 75 µm)

104
0.18 mm chip
PREAMPLIFIER
Gain 8mV/MIP 3.3V input trans 2000/0.5 gm
0.69 mS 40 mA (Weak inversion IC 0.01)
Tests results Gain
OK Linearity /-1.5 /-0.5 expected
Noise 3ms-20ms rise-fall, 40 mA 498
16.5 e-/pF OK Dynamic range
60 MIPs OK
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
105
0.18 mm chip
SHAPER
RC-CR Peaking time ajustable 1ms -gt 5ms
Tests 1.5 - 6 ms rise/fall Linearity /- 6
/- 1 expected Noise _at_ 3 ms 140mW power 375
10.4 e-/pF 274 8.9 e-/pF expected
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
106
Circuit en 0.13 mm
PREAMPLIFIER
Gain 28.5mV/MIP 3.3V transistor dentrée
1.5m/0.5mm gm 1.5 mS/ 70 mA Capacité de charge
133 fF Plage de dynamique 17MIPs (linearité
1 a 17MIPs) Bruit_at_70 mA 1000e- 25e-/pF
SHAPER
Filtre RC-CR Temps adjusté 0.7ms -gt
3ms bruit_at_700ns 33522e-/pF bruit_at_3ms
30516e-/pF Plage de dynamique 17MIPS
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
107
0.13 mm Chip Sparsifier
SPARSIFICATION
Sum of3 adjacent channels Résolution
0.1mV Response time 186ns
Offset cancel
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
108
0.13 mm Chip Simulations
SIMULATIONS
Preamps linearity
Shaper linearity
Sparsifier response
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
109
Possible issues Transistors leaks

• Two situations
• - Gate-channel due to tunnel effect (can
  affect noise performances)
• Through channel when transistor switched-off
  (only affects large digital designs)

Sub-threshold current

• - 180nm chip OK
• - 130nm, no gate
• leakage expected, but
• sub-threshold
• 90nm, important
• gate leakage
• Scale
• 1 nA/mm 8000 e- noise
• in FE

Nano-CMOS Circuit and Physical design B.P Wong,
A. Mittal, Y. Cao, G. Starr, 2005, Wiley
90 nm
130 nm
180 nm
Gate leakage
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
110
Possible issues noise 130nm vs 180nm
(simulation)

• PMOS

180nm gm944.4uS,gms203.1uS1MHz ?
3.508nV/sqrt(Hz)Thermal noise hand calculation
3.42nV/sqrt(Hz)
130nm W/L 2mm/0.5uIds 38.79u,Vgs-190mV,Vds-
600mVgm815.245u,gms354.118u1MHz ?
7.16nV/sqrt(Hz)Thermal noise hand calculation
3.68nV/sqrt(Hz)
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool
111
Noise 130nm vs 180nm(simulation)

• NMOS

130nm W/L 50u/0.5uIds48.0505u,Vgs260mV,Vds1.
2Vgm772.031uS,gms245.341uS,gds6.3575uS1MHz
--gt 24.65nV/sqrt(Hz)100MHz --gt
5nV/sqrt(Hz)Thermal noise hand calculation
3.78nV/sqrt(Hz)
180nm W/L50u/0.5uIds47uA,Vgs300mV,Vds1.2Vgm
842.8uS,gms141.2uS,gds16.05uS1MHz --gt
4nV/sqrt(Hz)10MHz --gt 3.49nV/sqrt(Hz)Thermal
noise hand calculation 3.62nV/sqrt(Hz)
Jean-François Genat 3d SiLC Workshop, June
13-14th 2006, Liverpool