Title: Vertex detector R
1Vertex detector RD Work Plan in 2004
- 2004/3/11
- Y. Sugimoto
- for
- KEK-Tohoku-TohokuGakuin-Niigata-ToyamaCMT
Collaboration
2Achievement in 2003
- Study of Radiation Damage
- Jul/Oct High energy electron irradiation at LNS
(Tohoku) - Electron energy dependence of CTI
- Observation of Hot Pixel generation by H.E.
electrons - Confirmation of effect of Fat-zero charge
injection - Study of charge diffusion in CCDs
- Measurement of Diffusion Time in CCDs
- Development of cPCI ADC DAQ System
- Thin CCD
- Ordered 4 types of small samples
3Mid-term Plan
- Milestone
- Construction of prototype sebsors and ladders
which can achieve an impact parameter resolution
of sb5 ? 10/(pbsin3/2q) mm - To achieve the target above we need study on
- Thinning of CCD wafers to minimize the multiple
scattering. The support structure for the thin
wafers is also needed - Radiation tolerance to put the detector as close
to the IP as possible. - Multiport readout of the CCD compatible with the
required readout speed of the vertex detector at
LC experiments. It also contributes to the
improvement of the radiation tolerance. - Readout ASIC for the multiport readout
- Preparation for the case that TESLA is selected
- 3-year project
- 1st year Basic Study
- 2nd yeat Detailed design of prototypes and make
an order - 3ed year Prototypes delivery and tests
4Mid-term Schedule
Original Plan Now(Hopefully)
Basic Study FY04 FY04 05 1H
Conceptual Design of Proto-type FY04 FY05 1H
Detailed Design of Proto-type FY05 1H FY05 2H
Order Mid FY05 FY05 End
Delivery Mid FY06 FY06 End
Test FY06 2H FY07 1H
5RD Items in 2004
- Thin Wafer
- Mechanical Strength
- Electrical Characteristics (Dark current, Speed)
- Impact on PhysicsSimulation (Efficiency, Purity,
Jet charge, etc) (1) - Radiation Tolerance
- CTI, DCP, Hot Pix Clock (F, tw, Amplitude)
dependence (2) - ? New driver board, Timing generator (FPGA), cPCI
DAQ system - Spatial Resolution vs. Radiation Damage (Using
LASER) (3) - Study of radiation tolerance of Back-thinned CCD
- ? Beam irradiation test ? or 90Sr irradiation is
OK? - Background Simulation (Particularly 2-photon b.g.
w/o Pt cut) (4) - (Readout ASIC Conceptual design)
- (Multi-port CCD Conceptual design)
- Preparation for the case of Cold Technology
(TESLA) - Study of diffusion in CCD back-thinned CCD
(LASER in H-Reg) (3) - Estimation of efficiencies when 50MHz r.o. is
impossible(High Hit density) Simulation (5)
6Thin Wafer
- Sample Chips (S7960-mod)
- Purpose Find the maximum cell size to keep
flatness - CCD format
- 24mm pixel size
- 256(H)x1044(H)
- 4-types with different cell size
- 4 bare chips and 8 packaged chips (4 types x 2)
- 2 standard packaged chips
- Schedule
- Mar. 2004 Bare chip delivery
- Apr. Flatness measurement ? Presented at Paris
(?)
7Radiation Immunity
- CCD
- Study on CCDs(256x256) irradiated in 2003
- New irradiation test will be done for S7960
(256x1044) (10 chips will be delivered) - Schedule
- By the end of June Set-up new readout system
- cPCI based DAQ
- New Driver Board
- FPGA Timing Generator
- July Intensive study ? Results by ACFA WS in
Nov.
8In case of Cold Technology
- No proven technology for VTX (except for thick
HAPS) - Fully Depleted CPCCD of Digital CMOS
- Fully Depleted CCD gt50MHz very challenging
- CMOS proposed by Yale group Direct encoding of
hit address - ? Very unique and may be promissing
- We have to make it clear if we can deal with
Cold before summer - Diffusion Study
- Hit density vs. Efficiency
- Study of CMOS
9Japan-US
- US Group SLD members?
- We can learn their know-how and experiences
- Different types of thinning and proto-types
between Japan and US? - Wider choice of the best technology
- Effective RD
- Evaluation and comparison of different types of
technology based on the common criteria - US group uses USJ budget for prototype sensors
DOE budget for others - Apply again in 2005 (unless US forsake us)
10World Wide Effort
- Future International LCMay not be GLC
- Physics Detector should be flexible
- Detector Component RD more and more
inter-regional - TPC EU, US, Japan
- CALICE Europe, US, ( Japan in future? )
- SILC EU, US, Korea, Tokyo U.
- Full Simulation requires a Detector Assembly
Model - Too early to start design of one (or 2) detector
in the world - Regional study based on Detector Models continue
- TESLA Detector
- US Large Detector
- US Small/Silicon Detector
- GLC Detector too conservative, not usable with
Cold - Need to re-construct New Detector Model in Asia?
11Proposal for New ACFA Advanced Detector Assembly
Model
GLC Detector Advanced Detector
Solenoid 3T 4T
Vertex Detector 4 layers (2460mm) 300mm thick sb7?20/(pbsin3/2q) 5 layers (1560mm) 100mm thick sb5?10/(pbsin3/2q)
Intermediate Tracker Si Strip Si Strip t-meas. Layer (SiFi) ?
Central Tracker Jet Chamber sPt/Pt1x10-40.1 TPC sPt/Pt0.5x10-40.1