Digital Electronics EEE3017W

1
Practical Logic Design

• Up until now, we have considered the different
  design methods and strategies from a mainly
  theoretical point of view
• When designing real circuits, it is vital to
  consider
• Timing
• Speed
• Cost
• Reliability
• We will now consider some practical digital
  design points

2
Digital Circuit Structure

• Digital circuits can be divided into two main
  structures
• Control Circuitry
• Data Flow Elements
• Data flow elements process data
• Control elements control the way in which this
  data is processed

3
Timing Diagrams
Taken from SN54HC00, SN74HC00 Datasheet (Texas
Instruments Semiconductor, 2003)
4
Unused Digital Inputs and Outputs
SN74HC00

• Consider the following component
• A 74HC00 Quad Dual input NAND gate
• You might design a circuit that only requires one
  gate
• This means that there are 3 NAND gates whose
  input and output pins will not be connected to
  anything
• What should we do with unused digital pins?

Texas Instruments Semiconductor (2003)
5
Unused Digital Inputs

• It is vital that all input pins are connected to
  either the positive supply (HIGH) or ground (GND)
• If a input pin is left floating, it is
• In an unknown state and can take on either a HIGH
  or a LOW value
• Susceptible to noise
• This results in unreliable chip behavior or
  simply the chip not working at all
• If the gate is not used then connect the pins to
  either a HIGH or a LOW
• Flip-Flops, counters etc Connect unused inputs
  to the inactive level
• If you use a NAND or a NOR gate as an inverter,
  do not connect all the inputs together as this
  can load the previous circuit. Rather connect
  unused inputs HIGH (NAND) or LOW (NOR)

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Unused Digital Outputs
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• Unused outputs can be left open circuit
• Outputs must not be tied together as this can
  result in a short if one is HIGH while the other
  is LOW
• Connect them to the appropriate logic such as an
  OR gate if needed

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7
Loading Outputs

• Often clock signals and reset signals are
  connected to many different inputs in a system
• Loading results in degradation of signal strength
  and the added capacitance results in clock skew

8
Loading Outputs cont.

• A digital output can be modeled as a voltage
  source and an internal resistance
• The load can be modeled as a capacitance
• If we apply a step change u(t) to the circuit we
  find that the output response will be
• This output is typically approximated as linear
  ramp
• Rise and fall times will change depending on the
  loading capacitance

9
Buffering Circuits

• A buffer is used to prevent a circuit from
  loading the output of another circuit by
  isolating the input from the output
• It typically has a gain of one
• The output tracks the input
• It has high input impedance and low output
  impedance
• It should have fast response time and a linear
  relationship between input and output
• To reduce signal loading it is often wise to
  include buffers which equalize the loading
  between circuits

10
Buffers cont.

• Here are two circuits that will cause problems
  due to unbalanced loading

Unequal Fanout causes clock skew and different
load dependant delays
Unequal Buffer Depth causes clock skew
11
Recommended Buffering

• Make sure that each line has the same number of
  buffers on it
• Ensure that there is the same fan out on all
  lines
• Make sure that the buffers are lightly loaded to
  ensure signal sharpness

12
System Resets

• It is important that there is some form of reset
  in digital circuits
• A system reset resets the whole system and can be
  used to
• Return the system to a known state
• Provide a known starting condition on system
  power up
• A reset system can be implemented using a
• External power on reset circuit
• Push Button
• Or both
• All resets pins should be connected to the same
  line so that all modules are reset at the same
  time

13
System Clocks

• A sequential circuits clock must be stable in
  order for the circuits operation to be reliable
• This means that there should be no unwanted
• Spikes
• Glitches
• Clipped pulse widths
• Additional pulses
• In order to avoid most of these problems, avoid
  gated clocks
• A gated clock is a clock signal that is combined
  with other signals using combinational logic
  (often an Enable signal)
• If gated clocks must be used, here are are some
  potential problems and solutions

14
Gated Clocks

• Consider these two circuits and the potential
  problems that can arise from gating clock pulses

• Note that these are only two examples of many
  problems that can arise from gating clocks

15
Recommended Gated Clock Design using Enable Pin

• If you wish to use the Enable (EN) pin to enable
  the clock signal
• Here is a suggested design strategy

16
Local Clocks
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• Local clock signals are generated from the logic
  circuit
• An example is a ripple counter
• This results in skewed clock signal caused by the
  propagation delay of the flip-flop
• This results in asynchronous design

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