Digital Electronics EEE3017W

1
Announcements

• Tutorial 1 booking sheets are on the digital lab
  notice board
• Lab 1 marks list is on the digital lab notice
  board

2
Clocking Strategies

• As discussed earlier, circuit speed is often
  critical in circuit design
• Double edged clocking is sometimes used to
  effectively double the clocking speed of the
  circuit without doubling the clock speed
• This uses both the rising and falling edges of
  the clock to trigger circuit events

3
Double edge clocking

• Problems with double edge clocking include
• Non-synchronous resetting
• Complex timing patterns make circuit analysis
  difficult
• Set up and hold times can be violated with fine
  tuned timing

4
Double edge clocking

• Recommended solution clock the circuit at twice
  the frequency

5
Level and Edge Triggered Devices

• A level triggered flip allows the state of the
  data input to be captured through out the entire
  active clock cycle
• How can this generate possible errors?

6
Level Triggered Devices

• Consider this design
• The d-type flip-flop is level triggered
• The output from the flip-flop is fed into a
  combinational logic circuit which feeds its
  signal back to the input

• This will cause the output to oscillate as long
  as the clock is active
• This is known as a Race Condition

7
Level Triggered Devices

• Consider this design
• A d-type flip-flop is used to capture the output
  of some combinational logic
• The flip-flop is level triggered
• Any possible variations on the input of the
  flip-flop will be propagated to the output
• The flip-flop acts as a transparent latch
• In most cases this is undesired behavior

8
Edge Triggered Devices

• For most synchronous design it is recommended
  that you use edge triggered devices

9
Summary of Design Rules

• Tie all unused input to the appropriate voltage
  level
• Keep designs synchronous by making asynchronous
  inputs synchronous if possible
• Use edge triggered devices
• Avoid gating clocks
• Always provide a system reset to set circuit to a
  known state

10
What have we covered in this Module?

• Basic Logic Gates
• De Morgan's Rules and General Boolean Identities
• Karnaugh Maps
• Combinational and Sequential Circuits
• Present State-Next State Diagrams
• Algorithmic State Machine Design
• One Flip-Flop per State
• Practical Logic Design Rules