LANSCE Timing Requirements LA-UR-03-3376

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LANSCE Timing RequirementsLA-UR-03-3376

• Eric Bjorklund

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Basic Characteristics

• Gate rather than Event driven system.
• 96 independent timing gates ? 82 gates in use.
• 8.3 millisecond machine cycle (120 Hz).
• 1 second super-cycle.
• Clock synchronized with ring RF.
• 2.7951389 MHz.

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Resolution, Accuracy, Stability

• Resolution 1 microsecond
• Accuracy ? 180 nanoseconds
• Stability (jitter) 30 nanoseconds

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Neutron Chopper and AC Line Coupling

• Maximum Slew Rate 0.3 Hz/second
• Maximum Drift ? 100 microseconds
• Accelerator Tracking Sigma 25 microseconds
• Chopper Tracking Sigma 330 nanoseconds

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Current Architecture
Timing Gates

• Star configuration
• 4 redundant gate generator sets in 2 CAMAC
  crates.
• Gate generators are loaded by Master Timer
  computer, then run independently.
• Master Timer computer checks the output of the
  gate generators and automatically switches to
  another set when a discrepancy is seen.

Timing Distribution
Master Timer
Timing Gate Generators
MUX
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Additional Requirements For Upgraded(Distributed)
System

• Front-end IOCs need some way to know which cycle
  they are currently in and when a cycle starts
• Front-end IOCs need some way to know the Flavor
  of the current cycle.