Detektoraufbau

1
TRD Coordination Meeting 15.4.2004
Volker Lindenstruth Chair of Computer Science
Kirchhoff Institute for PhysicsUniversity
Heidelberg, Germany Phone [phone]
4303 Fax [phone] Email ti_at_kip.uni-heide
lberg.de WWW www.ti.uni-hd.de
2
TRAP3 - status

• Known functional and timing bugs in trap2 fixed,
  several small improvements.
• JTAG circuit in TRAP3 simulated.
• Extensive readoutboard simulations done in 3
  different modes
• 17 chips (all functional)
• 3 chips, where the column merger with timing
  backannotation.
• 1 chip, different filter configurations with
  timing backannotation.
• In all cases the assembler program for linear fit
  and full readout was running on the chip.
• Improved software for creating the chip
  configuration for the readout board.
• DMEM bug (in trapadc) understood, fixed.
• ADC bugs found and fixed, power will be increased
• Worst case minimal clock period lt 8.1 ns (timing
  analysis).
• SUBMITTED !
• Wafer/MCM tester part selection and schematic
  entry.

3
21.05 mm
32.95 mm

• Reticle size 21.3 x 33 mm²
• Scribe Line width 175 µm
• Maximum possible Scribe Line 275 µm
• Design Size X 47.4 2.3 60.175 32.95 mm
• Design Size Y 45 60.175 21.05 m

4
TRAP3 wafer/MCM production tests

• Wafer test of TRAP3
• Measure the supply currents (not shown in the
  block diagrams).
• Test the digital part of the chip internally
  through the SCSN interface and pretrigger input.
• Apply stimuli to all ADC inputs (DDS on the block
  diagrams), read back through SCSN the event
  buffers and analyze RMS and ENOB of all ADCs.
• MCM test
• Measure the supply currents, the analog reference
  voltages.
• Apply stimuli to the PASA inputs and to the ADC
  direct inputs.
• Program test pulse in PASA.
• Digitize the PASA additional outputs using
  commercial ADCs at higher sampling rate 40 MHz.
• Digitize the PASA outputs by the trap ADCs,
  analyze the pulse shape, noise RMS (the later can
  be done on chip).
• Analyze the ENOB and RMS for the 3 direct ADC
  inputs.
• Send / receive data through the network links.
• Test the pretrigger and clock outputs.

5
TRAP3 wafer test
FPGA
SPI - serial interface, DDS direct digital
synthesis (fast DAC with built in LUT for sinus)
6
MCM production test
FPGA
7
TRD Integration Schedule