Sequential Statements and Sequential Circuit Design

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Sequential Statements and Sequential Circuit
Design

• Session - III

Prof. B V Uma, RVCE, Bangalore
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Contents

• Generate statement in structural model
• Signals, Variables and constants
• Brief of Sequential statements
• Process statement
• If then Else statement, D flipflop, JK flipflop
  using If then Else statement
• Case statement, 41 MUX using Case statement

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Component Instantiation

• begin
• FA0 FULLADDER
• port map (a(0), b(0), Cin, sum(0), c(1))
• FA1 FULLADDER
• port map (a(1), b(1), C(1), sum(1), c(2))
• FA2 FULLADDER
• port map (a(2), b(2), C(2), sum(2), c(3))
• FA3 FULLADDER
• port map (a(3), b(3), C(3), sum(3), c(4))
• Cout lt c(4)
• end fouradder_structure
• Internal signals c(4 downto 1) indicates the nets
  that connect the output carry of previous full
  adder to the input carry of the next full adder.

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Generation of Instances

• Some repetitive structure descriptions may be
  done with the generate statements, which allow
• 1. repetition of structures corresponding to the
  for...loop.
• 2.selection of specific instantiations through
  the if...then conditions.
• Syntax generate_label for variable in range
  generate   concurrent_statement   general
  instantiations end generate generate_label
  generate_label if (condition) generate
    concurrent_statement end generate
  generate_label

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Component Instantiation using Generate

• architecture fouradder_structure of FOURBITADD is
  
• signal c std_logic_vector (4 downto 0)
• component FULLADDER
• port(x, y, ci in std_logic s, co out
  std_logic)
• end component
• Begin
•   C(0) lt Cin   GF for I in 0 to 3 generate
      UX FULLADDER
• port map (a(i), b(i), C(i), sum(i),
  C(i1))
•   end generate   Cout lt c(4)
• end stru1

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Shift Register using D Flip Flop
Figure 3 Shift Register (SISO)
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Shift Register Using Iterative Construction
(Generate)

• entity SHIFT is port (  SIN, CLK in bit
          SOUT out bit) end SHIFT
  architecture stru1 of SHIFT is component DFF
      port (D, CLK in bit Q out bit) end
  component   signal Z bit_vector (0 to 4)
  begin   Z(0) lt SIN   GF for I in 0 to 3
  generate     UI DFF port map (Z(I), CLK,
  Z(I1))   end generate   SOUT lt Z(4) end
  stru1

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Selection of Specific Instantiations through the
if...then Conditions

• architecture stru2 of SHIFT is   component DFF
      port (D, CLK in bit Q out bit)   end
  component   signal Z bit_vector (1 to 3)
  begin   GF for I in 0 to 3 generate     GI1
  if (I 0) then generate       U0 DFF port map
  (SIN, CLK, Z(I1)) end generate

Cont
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• GI2 if ((I gt 0) and (I lt 3)) then generate
        UI DFF port map (Z(I), CLK, Z(I1))
      end generate          GI3 if (I 3)
  generate       U3 DFF port map (Z(I), CLK,
  SOUT)     end generate   end generate end
  stru2

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Data Objects Signals, Variables and Constants

• Signal
• Syntax
• signal list_of_signal_names type initial
  value
• Examples
• signal SUM, CARRY std_logic
• signal DATA_BUS bit_vector (0 to 7)
• signal VALUE integer range 0 to 100

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• Signals are updated after a delta delay.
• Example
• SUM lt (A xor B)
• The result of A xor B is transferred to SUM after
  a delay called simulation Delta which is a
  infinitesimal small amount of time.

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Constant

• Syntax
• constant list_of_name_of_constant type
  initial value
• Examples
• constant RISE_FALL_TME time 2 ns
• constant DELAY1 time 4 ns

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Variable

• Syntax
• variable list_of_variable_names type initial
  value
• Examples
• variable VAR1 boolean FALSE
• variable STS_BIT bit_vector (7 downto 0)

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• The variable is updated without any delay i.e. as
  soon as the statement is executed.
• Variables must be declared inside a process.

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Example of a process using Variables

• architecture VAR of EXAMPLE is
• signal TRIGGER, RESULT integer 0
• begin
• process
• variable x1 integer 1
• variable x2 integer 2
• variable x3 integer 3
• begin
• wait on TRIGGER
• x1 x2
• x2 x1 x3
• x3 x2
• RESULT lt x1 x2 x3
• end process
• end VAR

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• x1, x2 and x3 are computed sequentially and
  their values are updated instantaneously.
• The RESULT is computed using the new values of
  these variables.
• x1 2, x2 5 (ie23), x3 5. Since RESULT is a
  signal it will be computed at the time TRIGGER
  and updated at the time TRIGGER Delta. Its
  value will be RESULT12.

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Example of a process using Signals

• architecture SIGN of EXAMPLE is
• signal TRIGGER, RESULT integer 0
• signal s1 integer 1
• signal s2 integer 2
• signal s3 integer 3
• begin
• process
• begin
• wait on TRIGGER
• s1 lt s2
• s2 lt s1 s3
• s3 lt s2
• RESULT lt s1 s2 s3
• end process
• end SIGN

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• The signals will be computed at the time TRIGGER.
  
• All of these signals are computed using the old
  values of s1, s2 and s3.
• All the signals will be updated at Delta time
  after the TRIGGER has arrived.
• s12, s24 (i.e. 1(old value of s1)3), s32(old
  value of s2) and RESULT 123 6.

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Comparison between Signal and Variable
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Sequential Statements

• Statements that may only be used in the body of a
  process.
• Sequential statements are executed one after the
  other as they appear in the design from the top
  of the process body to the bottom sequentially..
• A process is constantly switching between the two
  states
• (1) the execution phase in which the process is
  active (statements within this process are
  executed),
• (2) the suspended state.

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Syntax

• process (sensitivity_list)   proc_declarativ_par
  t
• begin   sequential_statement_part end process
  proc_label
• The sensitivity_list is a list of signal names
  within round brackets, for example (A, B, C).

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• A process, becomes active by an event on one or
  more signal belonging to the sensitivity list.
• All statements between the keywords begin and end
  process are then executed sequentially.

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VHDL model for D flip flop

• library ieee
• use ieee.std_logic_1164.all
• entity dff is
• Port ( clk,d in std_logic
• Q, Qb out std_logic)
• end dff

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• architecture behdff of dff is
• Begin
• process(clk)
• begin
• If (clk1) then
• Q lt d
• Qb lt not (d)
• End if
• End process
• End behdff

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Nested Ifs and Elsifs
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VHDL Code for nested if elsif

• if (C1) then S1S2
• Elsif(C2) then S3S4
• Elsif(C3) then S5S6
• Else S7S8
• End if

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J-K flip-flop model using nested elsif
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VHDL code for JK Flip Flop(using nested elsif)

• (a) Using characteristic equations for J and K
• library ieee
• use ieee.std_logic_1164.all
• entity jkff is
• Port ( CLK, S, R, J, K, in std_logic
• Q, Qb inout std_logic)
• end jkff

Cont
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• architecture jkff1 of jkff is
• Begin
• process(S,R,CLK)
• begin
• if (R0) then Qlt0
• elsif(S0) then Qlt1
• elsif(CLK0 and CLKevent) then
• Qlt(J and not Q) or (not K and Q)
• end if
• End process
• Qblt not Q
• End jkff1

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(b) VHDL code for JK flip flopusing truth table

• library ieee
• use ieee.std_logic_1164.all
• entity jkff is
• Port ( clk, pr, cr, j, k in std_logic
• q, qb out std_logic)
• end jkff

Cont
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• architecture Behavioral of jkff is
• signal t std_logic
• begin
• process(clk,pr,cr)
• begin
• if(pr'0' and cr'1') then tlt'1'
• else if(pr'1' and cr'0') then tlt'0'
• else if (pr'1 and cr'1') then
• if(clk'event and clk'1') then
• if(j'0' and k'0') then tltt
• elsif(j'1' and k'0') then tlt'1'
• elsif(j'0' and k'1') then tlt'0'
• elsif(j'1' and k'1') then tltnot (t)
• end if
• end if end if end if end if
• qltt qbltnot (t)
• end process
• end Behavioral

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case statement

• Syntax
• case expression is   when choices gt
  sequential_statements   when others gt
  sequential_statements end case

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VHDL code for 41 MUX

• library ieee
• use ieee.std_logic_1164.all
• entity mux is
• Port ( i in std_logic_vector(3 downto 0)
• s in std_logic_vector(1 downto 0)
• y out std_logic)
• end mux

Cont
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• architecture Behavioral of mux is
• begin
• process(s,i)
• begin
• case s is
• when "00"gt ylti(0)
• when "01"gt ylti(1)
• when 10"gt ylti(2)
• when "11"gt ylti(3)
• when others gtylt'X'
• end case
• end process
• end Behavioral

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THANK YOU