IKI10201 06cSynthesis of Sequential Logic

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IKI10201 06c-Synthesis of Sequential Logic

• Bobby Nazief
• Semester-I 2005 - 2006

• The materials on these slides are adopted from
• Prof. Daniel Gajskis transparency for Principles
  of Digital Design.

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Analyze this!
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Remember sequential circuit analysis

• To analyze sequential circuits, you have to
• Find Boolean expressions for the outputs of the
  circuit and the flip-flop inputs.
• Use these expressions to fill in the output and
  flip-flop input columns in the state table.
• Finally, use the characteristic equation or
  characteristic table of the flip-flop to fill in
  the next state columns.
• The result of sequential circuit analysis is a
  state table or a state diagram describing the
  circuit.

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The Analysis
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Finite State Machine (FSM) Model

• Quintuple ltS,I,O,f,hgt
• S set of states
• I set of inputs
• O set of outputs
• f next-state function (S x I ? S)
• h output funtion
• state-based (Moore Machine) S ? O
• input-based (Mealy Machine) S x I ? O

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Moore Machine
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Mealy Machine
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FSM Implementations
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Synthesis of sequential logic
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The Case Modulo-3 Up-Down Counter
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FSM Model Capture
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FSM Model Capture (cont.)
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FSM Model Capture (cont.)
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State Minimization

• Reduce the number of states
• reduce the number of flip-flops
• Based on behavioral equivalence concept
• 2 FSMs are equivalent if they produce the same
  sequence of output symbols for every sequence of
  input symbols
• s1 s2 states in an FSM are equivalent, iff
• for every input symbol i, h(s1, i) h(s2, i)
• for every input symbol i, f(s1, i) f(s2, i)
• Minimization procedure
• partition states into equivalence classes
• construct new FSM with one state for each
  equivalence class

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State Minimization (cont.)
output values
next states
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State Minimization (cont.)

• State minimization can also be done using
  Implication Table (see text!)

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State Encoding

• The cost delay of FSM implementation depends on
  encoding of symbolic states.
• e.g., 4 states can be encoded in 4! 24
  different ways
• There are more than n! different encodings for n
  states.
• exploration of all encodings is impossible,
  therefore heuristics are used
• 3 different heuristics
• minimum-bit change
• prioritized adjacency
• hot-one encoding

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State Encoding (cont.)

• Minimum-bit change assigns codes to states so
  that the total number of bit changes for all
  state transitions is minimized.

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State Encoding (cont.)

• Prioritized adjacency assigns adjacent encodings
  to all states with common source, common
  destination, or common output
• Highest states with the same next-state since
  the same next-state code will appear in adjacent
  entries in the K-map
• Second the next-states of the same state since
  they also may appear adjacent in the K-map
• Third states that have the same output value for
  the same input value since they may be adjacent
  in the output K-map

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State Encoding (cont.)

• Possible state encoding for module-3 counter
• A minimum-bit change/prioritized adjacency
• B simplified output logic
• C Hot-one encoding

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State Encoding (based on Encoding A)
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Choice of memory elements

• Select the type of flip-flops from D, SR, JK, T
• Derive the required flip-flops input value for
  every present-next state pair then derive the
  excitation equations

J1 Q0CD Q0CD (C Q0D Q0D) K1
C J0 Q1CD Q1CD (C Q1D
Q1D) K0 C
J1 K1 J0 K0
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The Circuit Modulo-3 Up-Down Counter