INO TRIDAS presentations

1
INO TRIDAS presentations

• INO TRIDAS activities at Mumbai
• B.Satyanarayana
• DAQ system for INO prototype
• S.S.Upadhya
• Overview of nuclear instrumentation in
  Electronics Division, BARC
• Shanti Krishnan
• ASIC development in Electronics Division, BARC
• V.B.Chandratre

2
INO TRIDAS activities at Mumbai

• B.Satyanarayana
• TIFR, Mumbai
• bsn_at_tifr.res.in

3
Working groups

• At TIFR
• K.S.Gothe, Atul Jain, S.D.Kalmani, P.Nagaraj,
  B.K.Nagesh, S.K.Rao, L.V.Reddy, B.Satyanarayana
  and S.S.Upadhya
• At BARC
• V.B.Chandratre and Shanti Krishnan

4
TRIDAS strategies

• Test stand for detector R D
• Instrumentation for prototype detector
• R D and prototyping for full scale detector

5
Test stand for detector R D

• VME based hardware from CAEN
• Configuration
• 21-slot 9U crate with CERN approved backplane
• Power PC 604R 400 MHz controller, SCSI HD,
  Ethernet and console ports, Lynx-OS
• VME modules
• Scaler, I/O register, latch, qADC and TDC
• Current status
• System configured and setup
• Basic readout trials and software development
  under progress

6
Instrumentation for prototype detector

• Detector size 1m X 1m X 1m
• 6cm thick absorber, 1cm thick detector
• 14 detector layers, 28 detector readout planes
• 50(20) strips or channels per readout plane for a
  pitch of 20(50)mm
• Total channels are 1400(560)
• Components Discriminators, latches, TDCs,
  Trigger, Monitoring etc.

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Instrumentation for prototype detector (Cond.)

• Approach
• Use available resources and expertise
• Quick solutions and short term goals
• CAMAC based!
• Two schemes developed
• Non-FPGA based solution (S.S.Upadhya)
• FPGA based solution (Shanti Krishnan)
• To converge on one scheme soon (here!) and
  implement

8
RD and prototyping for full scale detector

• Procurement of VLSI design tools at TIFR
• Market survey in progress, indent to be placed
  soon
• BARCs expertise to be utilised
• ASIC development and prototyping activity
• V.B.Chandratre
• Small sub-groups working on various sub-systems
  such as VME hardware design, trigger, high
  voltage, slow control and monitoring, gas system,
  software etc.

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Summary

• Two proposed schemes
• FPGA based
• Non-FPGA based
• Both are technically feasible
• Time available for implementation is the decisive
  factor
• Some concerns on this issue for the FPGA approach
• _ Mixed scheme approach

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Action plan for prototype

• Design of front-end electronics
• Detailed design of the DAQ system
• Identify sub-tasks, assign responsibilities, work
  in parallel
• New materials, equipment required, place orders
• Preparing existing hardware
• Crates, controllers, TDCs, scalers etc.
• Prototyping, PCB designs etc
• Debugging and testing
• Integration issues

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Other important issues

• Setting up design infrastructure
• Initiation of future work
• BARCs ASIC programme
• Identifying, funding, working together on areas
  of common interest
• Long time scales, needs long lead times
• Existing other spin offs for this activity

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And finally .

• Weekly meetings of eTRIDAS team
• Monthly reviews
• A workshop at an appropriate time
• Minutes on INO official web site
• Feedback to
• bsn_at_tifr.res.in