Digital Timing and Carrier Synchronization

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Digital Timing and Carrier Synchronization

• Paul Husted
• Professor Robert Brodersen

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Motivation

• Increased Algorithm Complexity
• Designed to Better Utilize Channel
• Requires Very Accurate Synchronization
• Low Power Requirements
• Preserve Battery Life for Mobile Applications
• Low Power CMOS Digital Design Capability
• Increased Digital Circuitry Reduces Analog
  Complexity to Save Power

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System Specifications

• Direct Sequence CDMA System
• Data Uses Length 31 MLSR Code
• Up to 31 Users May Transmit Simultaneously
• Chip Rate of 25 MHz
• QPSK Symbols Allow Bit Rate of 1.61 Mbit/s
• System Assumes 15 dB SNR
• Allows 10-5 BER
• Max 100 ns Channel Length Assumed

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Pilot Sequence

• Pilot Sequence Transmitted Periodically
• Uses Unmodulated Length 31 MLSR Code
• Interacts with Data Code as Gold Code
• Multiple (10-15) Repetitions of MLSR Code
• Pilot Sequence Allows
• Carrier Offset Estimation
• Symbol and Chip Timing Determination
• Packet Synchronization

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Sigma-Delta A/D

• Oversampled Converter Uses Decimation Filterting
  to Provide Output
• 25 Msample/sec (200 Mhz Oversample Rate)
• 10 bits
• Additional Decimation Filters Used
• Provide 8 Evenly Spaced 25 Ms/sec Streams
• Digital Circuitry Chooses Best Stream
• Combining Streams Leads to Lower SNR

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Synchronization Block Diagram
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Pilot Detection

• 3 Evenly Spaced Streams Passed Through Pilot
  Matched Filter
• Dual Threshold System Detects Pilot
• Pilot Code Correlation Value Must Exceed
  high_thresh
• Sum of Pilot Code Correlation Values Between
  Peaks Must be Below low_thresh
• Second In-Phase Correlation Value Must Again
  Exceed high_thresh
• Variable Thresholds Set Based on Received Signal
  Power Estimate

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Pilot Detection - cont.

• Adaptive Thresholds Found Empirically
• Many Thanks to Andy!

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Pilot Detection cotd.

• Attempt to Ensure Extremely Low Probability of
  False Pilot Detection
• Missed Detection May Lead to Packet Loss
• False Pilot Detection
• May Temporarily Cause Loss of Synchronization
• May Cause Loss of Multiple Packets
• Probabilities of Missed Detection and False Alarm
  Depend on Channel Conditions

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Fine Timing and Carrier Synch

• MACs Borrowed from Correlator for
• Carrier Offset Estimate Determined
• Initially, ? 1 ? 1
• In Steady State, ?n ?n-1 ? n
• Accumulator Creates Opposite Rotating Phasor

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Length of Pilot Symbol

• The Variance of the Frequency Estimation is
  Determined by
• L Length of Observation Window
• D Spacing Between Observed Values

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Frequency Estimation Results

• Measured Values vs. Theory

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Digital Phase Locked Loop

• Data-Aided Mode
• Creates Coherent Mode During Pilot
• Decision Directed Mode Runs During Data

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Digital Phase Locked Loop cotd

• Phase updated as
• Linear Response When Close to Correct Phase
• Update Has Same Sign as Linear Detector
• Easy to Implement
• Does Not Require Lookup Table of Linear Detector

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Digital Phase Locked Loop cotd

• Loop Filter is Built as a 2 Tap FIR
• Phase Transfer Function Becomes
• FIR Not Restricted to be Monic
• Scaling of Tap Values Can Create Lowpass Filter
  with Sharp Cutoff

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CORDIC Blocks

• Angle Estimator
• Takes Real and Imaginary Components from Carrier
  Offset Estimator as Inputs
• 8-stage Recursive in 4 cycles
• Output to a Accumulator to Simulate Rotating
  Phasor
• Rotator
• Rotates Chosen Stream by Sum of DPLL Phase Update
  and Accumulator Phase Update

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Correlator

• Multi-User Detection (MUD) System
• Adapts to Environment
• Multipath Gain Estimates
• Correlation to Other Users
• Significantly Improves Performance
• Non-Adaptive Correlator
• Uses Fixed /-1 Tap Values
• Easier to Implement
• Implemented on this Test Chip

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Conclusion

• Low Power Synchronization Design
• Additional Digital Circuitry Allows for Less
  Complex Analog Circuitry
• Free Running Oscillator instead of VCO
• Relaxed Requirements for Analog Components
• Digital Circuitry Uses Less Power than Analog
• MACs Time Multiplexed from MUD
• Packet Style System for Networks
• Compensates for Indoor Channel