Lecture 7 Delays and Timing in Multilevel Logic Synthesis

1
Lecture 7Delays and Timing in Multilevel Logic
Synthesis

• Hai Zhou
• ECE 303
• Advanced Digital Design
• Spring 2002

2
Outline

• Gate delays
• Timing waveforms
• Performance calculations
• Static/dynamic hazards and glitches
• Designs to avoid hazards
• READING Katz 3.3, 3.4, 3.5.2, Dewey 6.5.1, 6.5.2

3
Time Response in Combinational Networks
emphasis on timing behavior of circuits
waveforms to visualize what is happening
simulation to create these waveforms
momentary change of signals at the outputs
hazards can be useful pulse shaping
circuits can be a problem glitches
incorrect circuit operation
Terms
gate delay time for change at input to cause
change at output minimum delay vs.
typical/nominal delay vs. maximum delay
careful designers design for the worst
case! rise time time for output to transition
from low to high voltage fall time time for
output to transition from high to low voltage
4
Concepts of Delays and Timing

• For a given gate, the gate delay refers to the
  time it takes the output signal to respond to in
  input transition

output
input
5
Gate Delays

• Why is there a gate delay?
• There are actual resistances and capacitances
  inside digital logic
• If you apply a unit step voltage signal to an
  input, the output will not respond immediately,
  but after a delay proportional to R.C

T delay R.C
Resistance of driver
Capacitance of load
Output
Input
6
Delays in Combinational Logic
Input transition
Output transition
QUESTION After the input goes from low to
high how long does it take for the output to go
from low to high (note depends on other inputs
being 1 or 0)
ANSWER Use simple delay models for each gate
and add up delays in a path from input to output
7
Delays in Combinational Logic
Low drive
Delay (nsec)
High drive
Wire load Capacitance C
Load capacitance (pF)
8
Designing Logic With High Performance
Reduce high load due to fanout
Higher drive gate
Input transition
QUESTION Suppose the delay from input to output
is 30 nsec and is unacceptable. How would you
make a higher performance design? ANSWER Reduce
capacitances at various loads, or use higher
drive gates
9
Gate Delays for Typical TTL Families
Delays in nano-seconds
10
Gate Delay Specifications
Example gate delays in nanoseconds for LSI Logic
1.5 micron gate array 2 input AND gate.
tpLH Propagation delay from low to high
transition at output tpHL Propagation delay
from high to low transition at output
11
Pulse Shaping Circuit
A
B
C
D
F
100
D remains high for three gate delays after A
changes from low to high
F is not always 0, pulse width equals 3 gate
delays
12
Another Pulse Shaping Circuit

Resistor
A
B
Open
C
D
Switch
Close Switch
Open Switch
Initially undefined
A B C D
13
Hazards and Glitches
Unwanted switching at the outputs Occur because
delay paths through the circuit experience
different propagation delays Danger if logic
"makes a decision" while output is unstable
OR hazard output controls an asynchronous input
(these respond immediately to changes
rather than waiting for a synchronizing
signal called a clock) Usual solutions
wait until signals are stable (by using a
clock) never, never, never use circuits
with asynchronous inputs design
hazard-free circuits Suggest that first two
approaches be used, but we'll tell you about
hazard-free design anyway!
14
Kinds of Hazards
1
1
Input change causes output to go from 1 to 0 to 1
0
1
Input change causes output to go from 0 to 1 to 0
0
0
1
1
0
0
Input change causes a double change from 0 to
1 to 0 to 1 OR from 1 to 0 to 1 to 0
1
1
0
0
Kinds of Hazards
15
Example of a Glitch
A
AB
00
01
11
10
CD
1
1
A
A
1
1
0
0
1
1
00
G1
G1
\C
\C
1
1
1
1
G3
F
G3
F
0
0
\A
\A
1
1
1
1
01
G2
G2
D
D
0
0
D
1
0
1
1
0
0
11
ABCD 1101
ABCD 1100
C
input change within product term
0
0
0
0
10
B
F A' D A C'
0
0
1
A
A
0
A
0
1
G1
G1
G1
\C
\C
\C
0
1
1
1
1
1
G3
F
G3
F
G3
F
0
0
1
\A
\A
\A
G2
G2
G2
D
D
D
0
0
1
1
1
1
ABCD 0101 (A is still 0)
ABCD 0101 (A is 1)
ABCD 1101
input change that spans product terms output
changes from 1 to 0 to 1
16
Eliminating Glitches
General Strategy add redundant terms
F A' D A C' becomes A' D A C' C' D
This eliminates 1-hazard? How about 0-hazard?
A
AB
Express F in PoS form F (A' C')(A
D) Glitch present! Add term (C' D)
00
01
11
10
CD
0
0
1
1
00
1
1
1
1
01
D
1
1
0
0
11
C
0
0
0
0
10
B
17
How to design Circuits without Glitches
Theorem Under the assumption of one input
switching, 2-level SOP has no 0-hazard and POS
has no 1-hazard.
Avoid 1-hazard in SOP all adjacent 1s
are covered by same products F A C' A' D
C' D Avoid 0-hazard in POS all adjacent 0s
are covered by same sums F (AC)(AD)(CD)
18
Dynamic Hazards
Example with Dynamic Hazard
1
\A
G1
B
Slow
G3
\B
G2
\C
G5
F
1
0
A
G4
\B
Three different paths from B or B' to output
ABC 000, F 1 to ABC 010, F 0 different
delays along the paths G1 slow, G4 very
slow
Handling dynamic hazards very complex Beyond our
scope
19
Summary

• Gate delays
• Timing waveforms
• Performance calculations
• Static/dynamic hazards and glitches
• Designs to avoid hazards
• NEXT LECTURE Latches and Flip-flops
• READING Katz 6