The Internal Organization of the CPU

1
The Internal Organization of the CPU
Physical MemoryRW
16
MMU

Bidirectional Tri State Buffer / Register
8
CS DS SS ES
8
8
16
8
8
MDR / MBR
MAR
8
8
8
8
8
8
8
8
8
8
8
8
IR
Iptr / PC
SP
Op1
Op2
8
General Purpose Register File
8
4
Control Unit
ALU
Result
Flag
2
The Internal Organization of the CPU

• 4. Special Purpose Registers consists of the
  following
• I. Four (4) Segment Registers each 8 bit
  Wide helps to implement Segmented Memory
  Management
• a) The Code Segment Register CS To access
  Code/ Text Segments .
• Programmer Inaccessible loaded by
  System Transition / Context Switch
• b) The Stack Segment Register SS To
  access Stack Segments needed during
• Calls Interrupts . Programmer
  Accessible .
• c) The Data Segment Register DS To
  access Non String Data Segments.
• d) The Extra Segment Register ES To
  access String Data Segments.
• Both the above registers are accessed
  normally via translator Directives / Under System
  ( Kernel) Mode
• ii. 16 bit Wide Stack Pointer (SP)
• Stack Address gt SS 8 bit SP 16
  bit Any byte among 2 8 number of 64 Kbytes
  Sized Stack Segments.
• iii. 16 bit Wide Program Counter (PC) /
  Instruction Pointer (IP)
• Instruction Address gt CS 8 bit
  PC / IP Any byte among 2 8 number of 64
  Kbytes Sized Data Segments .
• N.B. Any Data Address gt DS / ES 8 bit
  16 bit Memory Address ( depending on the
  Supported Addressing Modes . Any byte among 2
  Sets of 2 8 number of 64 Kbytes Sized Segments
  .

3
Peripheral Memory Interface - 1

• A. The Common external Gateway Takes Part in
  All types of External ( Peripheral / Memory )
  Access.
• A 16 bit Memory Address Register (MAR)
  Unidirectional cum Up Counter enables Operand
  Address accessing subsequent to Op Code Fetching
  loadable from the Group of 8 bit wide dedicated
  Segment Adders .
• An 8 bit Bi_ Directional Memory Data Register
  (MDR)
• / Memory Buffer Register (MBR) along with
  relevant input output control signals.
• The 24 bit Logical/ Virtual Address composed
  of 8 bit Segment Register Value Segment
  Selector appended by the 16 bit Address Offset
  being mapped to 16 bit Physical Memory Address by
  the Memory Management Unit MMU ( Dedicated
  Hardware / Software Module .

4
Peripheral Memory Interface - 2

• B. The Program Memory Interface
• A 8 bit Code Segment Register (CS)
  Programmer inaccessible .
• A 16 bit Instruction Pointer (IP) /
  Program Counter (PC) accessible in 2 Steps with
  provision for the following
• a) Incrementing by a specific amount
  (required to step through the instructions) aided
  by a dedicated PC Updater/ the same Segment
  Adder.
• b) Loading by the specific targets
  which can be obtained either
• (i) From the Data Bus due
  to
• a) A Control
  Instruction Operand from IR (Operand) .
• b) An Interrupt Vector
  From Peripheral Interface.
• c) ALU Result
  Addition / Subtraction of Relative Offset as
• specified in the
  IR (Operand) for Relative Jumping. . This also
  involves
• the ALU as well as
  ALL of its associated registers Flags.
• The 32 bit Instruction Register (IR) to be
  accessed in Multiple steps as it is connected
  to the 8 bit CPU UNI bus.

5
Peripheral Memory Interface - 3

• C. The Data Memory Interface
• A 8 bit Data Segment Register (DS) /
  Extra Segment Register (ES) Programmer
  accessible through Translator Directives /
  Privileged Instructions in O.S. Mode .
• The GPR File acting as either the Address
  Pointers (Register Indirect) / Base Value
  Index Values ( Based Indexed) along with 2 Port
  accessibility .
• The ALU its associated Operand Result
  Registers used for Address Calculation.
• The Instruction Register (IR)s Operand
  field(s).

6
Peripheral Memory Interface - 4

• C. The Stack Memory Interface
• A 8 bit Stack Segment Register (SS) User
  accessible .
• The 16 bit Stack Pointer (SP) with dedicated
  Incrementing / Decrementing facility.
• N.B Assumed that
• (i) The Mode Flag Content (M) 0 ? User
  Mode.
• (i) The Mode Flag Content (M) 1 ? System /
  Kernel Mode.

7
The Memory Address Register (MAR)
(Key Features)

• Provides a Common gateway between the CPU and
  external Address Bus.
• Segment Registers content are also routed
  through MAR.
• Accepts Segment Registers CS, DS, SS etc.
  contents directly through a dedicated line.
• 16 bit address offsets are loaded from the 8 bit
  CPU Uni-Bus itself in two consecutive cycles.
• Possible Sources
• 1) PC, SP, CPU GPRs.
• 2) Instruction Register Operand(s).
• 3) Stack Pointer.

8
The Memory Address Register (MAR)
To Memory Management Unit MMU

Address Bus
24
MARRD RD0
MAR 24 bit
INR
WR0
WR1
8
8
8
From PC / SP / Reg. Pair ( Loaded in 2 Steps)

From CS / SS / DS(ES)
9
The Memory Address Register (MAR) Operation
Control Table

• Operation
  WR1 WR0 RD0 INR
• MAR ? Segment Reg. Lower Offset
• Byte
  0 1 0 0
• MAR ? Higher Offset Byte 1
  0 0 0
• Address Bus ? MAR 0
  0 1 0
• Increment MAR
  0 0 0 1
• 1.MAR input (The16 bit Offset Addresses) is
  loaded into it from some register within the CPU
  itself.
• 2. MAR output is tri stated since Address Bus may
  be shared by Direct Memory accessing devices
  (DMA).

10
The Memory Data Register (MDR) / Memory Buffer
Register (MBR) (Key Features)

• Bi Directional Tri-State Buffer.
• Any CPU Register gets loaded from Memory via this
  register.
• Any CPU Register gets stored into Memory via this
  register.

11
The Memory Data / Buffer Register (MDR / MBR )
8
DATA BUS
8
8
Tri State Control
OUT MBR RD2
2 1 Group MUX
MDR / MBR
8
Select 1 -gt DATA BUS 0 -gt CPU BUS
8
WR1
8
8
Read MBR RD1
Tri State Control
8
CPU Internal Bus
12
The MDR / MBR Operation Control Table

• Operation Control Signal Status
• Performed Select WR1 RD1
  RD2
• Data Bus ? MDR 1
  1 0 0

MDR ? CPU Bus 0
0 1 0
CPU BUS ? MDR 0
1 0 0
MDR ? Data Bus 0
0 0 1
13
The Program Counter / PC
CPU Internal Bus

8
8
8
8
8

LOAD
LOAD
2- 1 8 bit Group MUX
2- 1 8 bit Group MUX
n
16 bits With Higher Order Bits 0
8
8
WRPCH
PC High
PC Low
Instruction Length Buffer
WRPCL
RDPCL
To CPU BUS
8
8
RDPCH
16 bit PC Incrementer ()
Cy_In 0
8
8
14
The Program Counter / PC Operation Control Table

• Operation WRPCH WRPCL RDPCH
  RDPCL LOAD
• PCH ? CPU Bus 1
  0 0 0 0
• PCL ? CPU Bus 0
  1 0 0 0
• PC ? PC Inst Length 0
  0 0 0 1
• CPU Bus ? PCL 0
  0 0 1 0
• CPU Bus ? PCH 0
  0 1 0 0

15
The 2 Port GPR File

Read/Output Addr Latch O3 O2 O1 O0
Write/Input Addr Latch I3 I2 I1 I0
Reg. Pair Access (INR)
From CPU Bus
Reg. Pair Access(INR)
GPRWRCLK
OLWCLK
ILWCLK
1 - 16 8 bit Group De MUX
16 1 8 bit Group Mux
r0
From CPU Bus
ri
Tri State
GPRRD
r15
To CPU Bus
8 Bit Data Bus
16
The 2 Port GPR File Operation Table

• Operation Write Addr OLWCLK Read Addr
  ILWCLK GPRWRCLK GPRRD
• (I3I2I1I0)
  (O3O2O1O0)
• r15 ? CPU Bus 1 1 1 1 1
  XXXX X
  1 0
• CPU Bus ? r8 XXXX X
  1 0 0 0 1
  0 1
• r14X ? CPU Bus 1 1 1 0 1
  XXXX X 1
  0
• Next Clk with 1 1 1 1 0
  XXXX X
  1 0
• Pair Access by INR
• CPU Bus ? r8X XXXX X
  1 0 0 0 1 0
  1
• Next Clk with XXXX X
  1 0 0 1 0
  0 1
• Pair Access by INR

17
The Segment Register File

SIn1 SIn0
SO1 SO0
SWCLK
8
8
1 - 4 8 bit Group De MUX
4 1 8 bit Group Mux
CS
From CPU Bus
8
8
8
DS
8
8
8
SS
To MAR
8
8
ES
18
The Segment Register File Operation Table
19
The ALU Associated Interface

• 1. UNI Bus i.e. a single, 8 bit wide CPU
  Internal Bus.
• 2.The ALU its associated interfaces are
  depicted below (all buses except buses connected
  to Flags are 8 bit wide)

8
8
8
Op 1
Op 2
ALU I1 WR
ALU I2WR
8
Function Code
8 bit ALU
ALUFLOAD
Result
Flags
ALUOUTRD
FLAGRD