The Internal Organization of the CPU

1
The Internal Organization of the CPU
Physical MemoryRW
32
MMU

Bidirectional Tri State Buffer / Register
16
CS DS SS ES
32
32
16
16
MDR / MBR
MAR
16
32
32
16
32
32
32
32
8
24
32
IR
Iptr / PC
SP
Op1
Op2
32
General Purpose Register File
8
Control Unit
ALU
Result
Flag
32
2
The Internal Organization of the CPU

• 4. Special Purpose Registers consists of the
  following
• I. Four (4) Segment Registers each 16 bit
  Wide helps to implement Segmented Memory
  Management
• a) The Code Segment Register CS To access
  Code/ Text Segments .
• Programmer Inaccessible loaded by
  System Transition / Context Switch
• b) The Stack Segment Register SS To
  access Stack Segments needed during
• Calls Interrupts . Programmer
  Accessible .
• c) The Data Segment Register DS To
  access Non String Data Segments.
• d) The Extra Segment Register ES To
  access String Data Segments.
• Both the above registers are accessed
  normally via translator Directives / Under System
  ( Kernel) Mode
• ii. 32 bit Wide Stack Pointer (SP)
• Stack Address gt SS 16 bit SP 32
  bit Any 32 bit Word among 2 16 number of 4
  Giga Word Sized Stack Segments.
• iii. 32 bit Wide Program Counter (PC) /
  Instruction Pointer (IP)
• Instruction Address gt CS 32 bit
  PC / IP Any 32 bit Word among 2 16 number of
  4 Giga Word Sized Data Segments .
• N.B. Any Data Address gt DS / ES 16 bit
  32 bit Memory Address ( depending on the
  Supported Addressing Modes . Any 32 Bit Word
  among 2 Sets of 2 16 number of 4 Giga Word
  Sized Segments .

3
Peripheral Memory Interface - 1

• A. The Common external Gateway Takes Part in
  All types of External ( Peripheral / Memory )
  Access.
• A 32 bit Memory Address Register (MAR)
  Unidirectional with dedicated Increment
  facility enables Operand Address accessing
  subsequent to Op Code Fetching loadable from the
  Group of 16 bit wide dedicated Segment
  Selector(s) .
• A 32 bit Bi_ Directional Memory Data Register
  (MDR)
• / Memory Buffer Register (MBR) along with
  relevant input output control signals.
• The 48 bit Logical/ Virtual Address composed
  of 16 bit Segment Register Value Segment
  Selector appended by the 32 bit Address Offset
  being mapped to 32 bit Physical Memory Address by
  the Memory Management Unit MMU ( Dedicated
  Hardware / Software Module .

4
Peripheral Memory Interface - 2

• B. The Program Memory Interface
• A 16 bit Code Segment Register (CS)
  Programmer inaccessible .
• A 32 bit Instruction Pointer (IP) /
  Program Counter (PC) accessible in 2 Steps with
  provision for the following
• a) Incrementing by a specific amount
  (required to step through the instructions) aided
  by a dedicated PC Updater/ Incrementer.
• b) Loading by the specific targets
  which can be obtained either
• (i) From the Data Bus due
  to
• a) A Control
  Instruction Operand from IR (Operand) .
• b) An Interrupt Vector
  From Peripheral Interface.
• c) ALU Result
  Addition / Subtraction of Relative Offset as
• specified in the
  IR (Operand) for Relative Jumping. . This also
  involves
• the ALU as well as
  ALL of its associated registers Flags.
• The 64 bit Instruction Register (IR) to be
  accessed in Multiple steps as it is connected
  to the 32 bit CPU UNI bus.

5
Peripheral Memory Interface - 3

• C. The Data Memory Interface
• A 16 bit Data Segment Register (DS) /
  Extra Segment Register (ES) Programmer
  accessible through Translator Directives /
  Privileged Instructions in O.S. Mode .
• The GPR File acting as either the Address
  Pointers (Register Indirect) / Base Value
  Index Values ( Based Indexed) along with 2 Port
  accessibility .
• The ALU its associated Operand Result
  Registers used for Address Calculation.
• The Instruction Register (IR)s Operand
  field(s).

6
Peripheral Memory Interface - 4

• C. The Stack Memory Interface
• A 16 bit Stack Segment Register (SS)
  User IN-accessible .
• The 32 bit Stack Pointer (SP) User Accessible
  with dedicated Incrementing / Decrementing
  facility.
• Two different Stacks namely USER as well as
  System/Kernel are employed during execution. User
  stack are used to store the Current Activation
  Record, Register Traces ( Last THREAD of
  execution)
• N.BIt has been already specified that
• (i) The Mode Flag Content (M) 0 ? User
  Mode.
• (i) The Mode Flag Content (M) 1 ? System /
  Kernel Mode.

7
The Memory Address Register (MAR)
(Key Features)

• Provides a Common gateway between the CPU and
  MMU.
• 32 bit address offsets are loaded from the 32 bit
  CPU Uni-Bus itself.

8
The Memory Address Register (MAR)
(Key Features)

• Provides a Common gateway between the CPU and
  Memory Management Unit (MMU).
• 32 bit address offsets are loaded from the 32 bit
  CPU Uni-Bus itself which in turn is fed to the
  MMU.
• The only source to access Operand Addresses
  AFTER fetching the 1st Part of an instruction.

9
The Memory Address Register (MAR)
(GATEWAY to MMU)

• Possible Sources
• 1) IPtr/PC Control Flow Instructions,
  Instruction Fetch
• 2) CPU GPRs Register Indirect Addressing
• 3) Instruction Register Operands Direct,
  Memory Indirect (if supported) Addressing .
• 4) ALU Result Based Indexed , PC Relative
  (if Supported) Addressing
• 3) Stack Pointer (SP). PUSH POP

10
The Memory Address Register (MAR)
To Memory Management Unit MMU

Address Bus
32
MAR 32 bit
MARRD
INR
MARWR
32
From PC / SP / GPR / ALU Result / IR (Operand)


11
The Memory Address Register (MAR) Operation
Control Table

• Operation
  WR RD INR
• MAR ? SP / PC / IR / GPR /ALU Result 1 0
  0
• MMU ? MAR 0
  1 0
• Increment MAR
  0 0 1
• 1.MAR input (The 32 bit Offset Addresses) is
  loaded into it from some register within the CPU
  itself.
• 2. MAR output is tri stated since MMU Bus may be
  shared by Direct Memory accessing devices (DMA).

12
The Memory Data/Buffer Register (MDR/MBR)
(GATEWAY to Outside World)

• Possible Participation in the following
  Activities
• 1) Instruction Fetch from Program Memory.
• 2) Operand Address Reading ( For Memory
  Indirect Addressing (if supported)
• 3) Data Reading from Memory/Peripheral .
• 4) Data Writing to Memory / Peripheral.

13
The Memory Data Register (MDR) / Memory Buffer
Register (MBR) (Key Features)

• Bi Directional Tri-State Buffer.
• Any CPU Register gets loaded from Memory via this
  register.
• Any CPU Register gets stored into Memory via this
  register.

14
The Memory Data / Buffer Register (MDR / MBR )
32
DATA BUS
32
32
Tri State Control
OUT MBR RD2
2 1 Group MUX
MDR / MBR
32
Select 1 -gt DATA BUS 0 -gt CPU BUS
32
WR
32
32
Read MBR RD1
Tri State Control
32
CPU Internal Bus
15
The MDR / MBR Operation Control Table

• Operation Control Signal Status
• Performed Select WR RD1
  RD2
• Data Bus ? MDR 1
  1 0 0

MDR ? CPU Bus X
0 1 0
CPU BUS ? MDR 0
1 0 0
MDR ? Data Bus X
0 0 1
16
The Program Counter / PC
CPU Internal Bus

32
32
32

2- 1 32 bit Group MUX
32
LOAD
n
32
PC High 16
PC Low 16
Instruction Length Info
WRPC
RDPC
32
To CPU BUS
32 bit PC Incrementer ()
Cy_In 0
32
17
The Program Counter / PC Operation Control Table

• Operation WRPC RDPC
  LOAD
• PC ? CPU Bus 1
  0 0
• PC ? PC Inst Length 0
  0 1 ( NOT NEEDED HERE)
• CPU Bus ? PC 0
  0 0

18
The 2 Port GPR File

Read/Output Addr Latch O4 O3 O2 O1 O0
Write/Input Addr Latch I4 I3 I2 I1 I0
Reg. Pair Access (INR)
From CPU Bus
Reg. Pair Access(INR)
GPRWRCLK
OLWCLK (Dest. Select)
ILWCLK (Source Select)
1 - 32 32 bit Group De MUX
32 1 16 bit Group Mux
r0
From CPU Bus(32 bit)
ri
Tri State
GPRRD
r31
To CPU Bus
19
The 2 Port GPR File Operation Table

• Operation Write Addr OLWCLK Read Addr
  ILWCLK GPRWRCLK GPRRD
• (I4I3I2I1I0)
  (O4O3O2O1O0)
• r15 ? CPU Bus 0 1 1 1 1 1
  XXXXX 0 1
  0
• CPU Bus ? r8 XXXXX 0
  0 1 0 0 0 1 0
  1
• r30 ? CPU Bus 1 1 1 1 0 1
  X XXXX 0 1
  0
• CPU Bus ? r30 XXXXX 0
  0 1 0 0 0 1 0
  1

20
The Segment Register Group

SIn1 SIn0
SO1 SO0
SWCLK
16
16
1 - 4 16 bit Group De MUX
4 1 16 bit Group Mux
CS
From CPU Bus
16
16
16
DS
16
16
16
SS
To MMU
16
16
ES
SEGRegRD
21
The Segment Register Group Operation Table

• Operation DeMux Select SWCLK MUX
  Select SEGRegRD
• (SIn1SIn0)
  (SOut1SOut0)
• --------------------------------------------------
  --------------------------------------------------
  ---------
• CS ? CPU Bus 0 0
  1 X X
  0
• --------------------------------------------------
  --------------------------------------------------
  ----------
• MMU (Seg) ? CS X X 0
  0 0
  1
• --------------------------------------------------
  --------------------------------------------------
  ---------
• DS ? CPU Bus 0 1
  1 X X
  0
• --------------------------------------------------
  --------------------------------------------------
  ---------
• MMU (Seg.) ? DS X X 0
  0 1
  1
• --------------------------------------------------
  --------------------------------------------------
  ----------
• SS ? CPU Bus 1 0
  1 X X
  0
• --------------------------------------------------
  --------------------------------------------------
  ----------
• MMU (Seg.) ? SS X X 0
  1 0
  1
• --------------------------------------------------
  --------------------------------------------------
  ---------------
• ES ? CPU Bus 1 1
  1 X X
  0
• --------------------------------------------------
  --------------------------------------------------
  -------------
• MMU (Seg.) ? ES X X 0
  0 1
  1

22
The ALU Associated Interface

• 1. UNI Bus i.e. a single, 32 bit wide CPU
  Internal Bus.
• 2.The ALU its associated interfaces are
  depicted below (some of which can be OMITTED) all
  buses except buses connected to Flags are 32 bit
  wide

32
32
32
Op 1
Op 2
ALU I1 WR
ALU I2WR
32
Function Code
32 bit ALU
ALUFLOAD
Result
Flags
ALUOUTRD
FLAGRD
23
Typical ALU Operation Sequence

• Load OP1 / OP 2 Register from CPU Bus. (
  Assert ALUIP1WR / ALUIP2WR) .
• Load OP2 / OP 1 Register from CPU Bus. (
  Assert ALUIP2WR / ALUIP1WR) may not be necessary
  even for UNI Bus.
• Assert ALU Function Code as dictated by the
  Instruction Op Code.
• Store Generated Result FLAGS.
• (Assert ALUOUTRD ALUFRD).