Fault Modeling

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Fault Modeling

• Original slides are modified by Fatih Kocan

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Lecture 5Fault Modeling

• Why model faults?
• Some real defects in VLSI and PCB
• Common fault models
• Stuck-at faults
• Single stuck-at faults
• Fault equivalence
• Fault dominance and checkpoint theorem
• Classes of stuck-at faults and multiple faults
• Transistor faults
• Summary

3
Why Model Faults?

• I/O function tests inadequate for manufacturing
  (functionality versus component and interconnect
  testing)
• Real defects (often mechanical) too numerous and
  often not analyzable
• A fault model identifies targets for testing
• A fault model makes analysis possible
• Effectiveness measurable by experiments

4
Some Real Defects in Chips

• Processing defects
• Missing contact windows
• Parasitic transistors
• Oxide breakdown
• . . .
• Material defects
• Bulk defects (cracks, crystal imperfections)
• Surface impurities (ion migration)
• . . .
• Time-dependent failures
• Dielectric breakdown
• Electromigration
• . . .
• Packaging failures
• Contact degradation
• Seal leaks
• . . .

Ref. M. J. Howes and D. V. Morgan, Reliability
and Degradation - Semiconductor Devices
and Circuits, Wiley, 1981.
5
Observed PCB Defects
Occurrence frequency () 51 1 6 13 6 8
5 5 5
Defect classes Shorts Opens Missing
components Wrong components Reversed
components Bent leads Analog specifications Digita
l logic Performance (timing)
Ref. J. Bateson, In-Circuit Testing, Van
Nostrand Reinhold, 1985.
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Functional vs. Structural Testing

• Testing of a 10-input AND function
• Apply 0101010101 , observe 0
• Correct output
• What is the gate under test? AND, not NAND, not
  NOR, not OR
• To make sure, gate is not a NOR
• Apply 1111111111
• Gate is AND
• Question will the gate function as AND for all
  210 inputs?
• Complete functional test check each entry for
  the truth table
• A circuit with 200 inputs, 2200 entry to check!

Correct answers
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Structural Test

• Observe the state of the internal signals at the
  primary outputs
• The tests depend on the specific structure of the
  circuit
• Ex gate level gates lines nets
• Advantage of structural tests
• Allow the development of ALGORITHMS!
• Central to these algorithms are FAULT MODELS
• Most test generation and fault simulation is
  based selected Fault Models

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Levels of Abstraction
Behavioral Description
While (igtj) A (dgtgt2)
Increasing level of abstarction
ROM
RAM
ALU
Functional Description (RTL)
Control
Structural Description
Switch-level Description
Geometric Description (layout)
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Inverter Layout
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Glossary of Fault Models

• Bridging Fault
• Model level (usually) gate or transistor level
• Representation a short between a group of
  signals
• Logic value of shorted net
• OR bridge 1-dominant, 0-dominant AND bridge,
  indeterminate
• Non-feedback bridging faults are combinational
  their coverage by stuck-at fault is high
• Feedback bridging faults produce memory states
• Bridging fault is example of defect-oriented
  fault

Bridging fault
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Bus Fault

• Bus fault specify the status for each line in a
  bus as stuck-at 0, stuck-at-1, fault free.
• n-bit bus 3n-1 bus faults
• total bus fault all lines to be stuck-at the
  same 0 or 1 state

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Defect-Oriented Faults

• Faults at the physical level
• Occurs during manufacture
• Electrical or logic-level faults that can be
  produced by physical defects are classified as
  defect-oriented faults.
• Examples of physical defects
• Broken (open) wires, bridges, improper
  semiconductor doping, improperly formed devices
• Some defect-oriented fault models bridging
  faults, stuck-open faults, increased IDDQ fault

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Delay Fault

• Cause the combinational delay of a circuit to
  exceed the clock period.
• Delay faults
• Transition faults, gate-delay fault, line-delay
  fault, segment delay fault, path delay fault

14
Initialization Fault

• Faults that interfere with the initialization of
  flip-flops in sequential circuits (memory
  elements) are called initialization faults.
• Examples clock stuck-at, set/reset stuck-at, or
  some other lines

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Logical Faults

• Faults that affect the state of the logic signals
• States 0,1,X (unknown), Z (high impedance)
• Fault transform the correct value to any other
  value, e.g. 0?1, 1?X
• Logical faults often imply stuck-at faults

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Memory Faults

• Single cell stuck-at 0,1 faults
• Pattern sensitive faults,
• Cell coupling faults
• Single stuck-at faults in the address decoder
  logic

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Multiple Fault

• Simultaneous presence of a group of SINGLE faults
• Usually, a group of the same fault type
• multiple stuck-at, multiply-testable path delay
• Practicality issues
• The number of multiple faults is high
• N faulty sites 3n-1 multiple stuck-at faults
• M paths 3M-1 multiply-testable path delay
  faults
• M exponential with circuit size, e.g. c6288
  220 paths, therefore, 3220 multiply-testable
  faults
• Tests for single stuck-at faults cover a very
  high percentage ( gt 99.6) of multiple stuck-at
  faults for VLSI circuits

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Multiple stuck-at faults

• Diagnostic procedure developed for single
  stuck-at fault assumption does not work well when
  multiple stuck-at faults present
• A circuit with redundant sing stuck-at faults can
  malfunction in the presence of a multiple fault
  even the circuit passes the test
• F1,F2,F3 are redundant!
• Multiply-testable stuck-at fault all single
  faults are redundant

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Multiple Faults

• Enhance the test to cover multiply-testable
  faults
• Make the circuit fully single fault testable by
  removing the redundant faults
• Fault masking a test ti for a fault fi fails to
  produce the fault effect at an observable output
  in the presence of another fault fj, then fj
  masks fi
• Circular fault masking two or more faults mask
  each other, very rare

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Potentially Detectable Fault

• Faults that produce an unknown state at the
  output when a deterministic output is expected in
  the fault-free circuit
• Potential (or probabilistic) detection
• Deterministic detection faulty and fault-free
  must be different and definite (0 or 1)

Potentially detectible fault
A s-a-0 is detected only if FF powers up in 1
state
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1-bit counter
Q
D
Q
C
R
s-a-1
A fault preventing initialization
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Race Fault

• (stuck-at) Faults that case a race condition
• Race condition for a certain initial state and
  input, the final state of an asynchronous
  sequential circuit can vary depending on the
  specific delays of its logic gates
• Simulator places UNKNOWN signal value when a race
  condition occurs
• The race fault may appear similar to
  initialization fault

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Redundant Fault

• Combinational Circuits
• Redundant faults do not modify the input-output
  function of the circuit
• Redundant fault cannot be detected by any test.
• Such faults can be removed from the circuit w/o
  changing the function (see circuit optimization)
• Redundant fault untestable fault
• Sequential Circuits
• Identification/removal of redundant faults are
  complex
• The faults for which no test can be found are
  UNTESTABLE FAULTS

untestable
redundant
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Untestable Faults

• A fault for which no test can be found
• 1) Redundant faults
• 2) faults that change the input-output behavior
  of the circuit but no test can be found by a
  given method of testing or test generation
• Initialization fault in seq. circuits

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Transistor (Switch) Faults

• MOS transistor is considered an ideal switch and
  two types of faults are modeled
• Stuck-open -- a single transistor is permanently
  stuck in the open state.
• Stuck-short -- a single transistor is permanently
  shorted irrespective of its gate voltage.
• Detection of a stuck-open fault requires two
  vectors.
• Detection of a stuck-short fault requires the
  measurement of quiescent current (IDDQ).
• Single fault assumption only one transistor is
  faulty.

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Stuck-Open Example
Vector 1 test for A s-a-0 (Initialization vector)
Vector 2 (test for A s-a-1)
VDD
pMOS FETs
Two-vector s-op test can be constructed
by ordering two s-at tests
A
1 0
0 0
Stuck- open
B
C

0
1(Z)
Good circuit states
nMOS FETs
Faulty circuit states
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Stuck-Short Example
Test vector for A s-a-0
VDD
pMOS FETs
IDDQ path in faulty circuit
A
Stuck- short
1 0
B
Good circuit state
C

0 (X)
nMOS FETs
Faulty circuit state
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CMOS NOR
S a short circuit between supply nodes

• Stuck-open s-a-1 at the input of p- transistor
• Stuck-short s-a-0 at the input of n-transistor

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Common Fault Models

• Single stuck-at faults
• Transistor open and short faults
• Memory faults
• PLA faults (stuck-at, cross-point, bridging)
• Functional faults (processors)
• Delay faults (transition, path)
• Analog faults
• For more examples, see Section 4.4 (p. 60-70) of
  the book.

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Single Stuck-at Fault

• Three properties define a single stuck-at fault
• Only one line is faulty
• The faulty line is permanently set to 0 or 1
• The fault can be at an input or output of a gate
• Example XOR circuit has 12 fault sites ( ) and
  24 single stuck-at faults

Faulty circuit value
Good circuit value
c
j
0(1)
s-a-0
d
a
1(0)
g
h
1
z
i
0
1
e
b
1
k
f
Test vector for h s-a-0 fault
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Fault Detection in Sequential Circuits

• (Usually) a sequence of test sequence is required
  to detect a fault
• The response of the circuit is a function of its
  initial state
• T test sequence, R(q,T) response qinitial
  state
• Nf circuit with fault f
• Rf(qf,T) response of Nf
• A test sequence T strongly detects the fault f
  iff the output sequences R(q,T) and Rf(qf,T) are
  different for every possible pair of initial
  states q and qf

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Strong Detection in Sequential Circuits
y1
y1
x
Q
y2
x
a s-a-1
y2
y1
D
y2
x
b s-a-0
y1
y2
clock
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Strong Detection in Seq. Circuits (cont.)
Fault a not strong detection Fault b strong
detection
Output sequence
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Issues detection

• List all possible responses of the normal and
  faulty machines
• Not practical , n FF ? 2n states
• Tester operation
• Edge-pin testing with full comparison of the
  output results
• Compare the obtained and expected output
  sequences on a vector-by-vector basis
• Expected output response must be known in advance
  
• Rf must be predictable
• A test sequence T detects the fault f iff for
  every possible pair of initial states q and qf,
  the output sequences R(q,T) and Rf(qf,T) are
  different for some specified vector tiT
• How to find ti ?
• Apply an initialization sequence (TI) to bring
  the circuits into known states, qIf and qI
• Ignore the responses to TI since they are
  unpredictable
• Apply T in the second phase
• Both R(qI,T) and Rf(qIf,T) are predictable
• ti is taken as the first vector of T for which
  an error is observed
• Assumption initialization sequence exists for
  faulty circuit

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Fault Equivalence

• Number of fault sites in a Boolean gate circuit
  PI gates (fanout branches).
• Fault equivalence Two faults f1 and f2 are
  equivalent if all tests that detect f1 also
  detect f2.
• Functionally equivalent under a test set T iff
  Zf(f)Zg(f) for every test tT
• If faults f1 and f2 are equivalent then the
  corresponding faulty functions are identical.
• Fault collapsing All single faults of a logic
  circuit can be divided into disjoint equivalence
  subsets, where all faults in a subset are
  mutually equivalent. A collapsed fault set
  contains one fault from each equivalence subset.

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Equivalence Rules
sa0
sa0
sa1
sa1
WIRE
AND
OR
sa0
sa1
NOT
sa0
sa1
sa0 sa1
sa0 sa1
sa0
NAND
NOR
sa1
sa0
sa0 sa1
sa1
sa0
sa1
FANOUT
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Equivalence Example
sa0 sa1
Faults in red removed by equivalence collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20 Collapse ratio
----- 0.625 32
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Fault Collapsing by Functional Equivalence

• Two faults result in the same function

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Functional Equivalence in Sequential Circuits

• Two faults f and g are strongly functionally
  equivalent iff the corresponding sequential
  circuits Nf and Ng have equivalent state tables
• Practical def two faults f and g are said to be
  functionally equivalent iff Rf(qIf, T)
  Rg(qIg,T) for any T.
• TI initialization sequence (responses are
  ignored)
• T propagation sequence

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Fault Dominance

• If all tests of some fault F1 detect another
  fault F2, then F2 is said to dominate F1.
• Dominance fault collapsing If fault F2 dominates
  F1, then F2 is removed from the fault list.
• When dominance fault collapsing is used, it is
  sufficient to consider only the input faults of
  Boolean gates. See the next example.
• In a tree circuit (without fanouts) PI faults
  form a dominance collapsed fault set.
• If two faults dominate each other then they are
  equivalent.

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Fault f dominates g
Tf
Tg subset of Tf
Tg
A test that detects fault g will detect fault f
also. Why would we generate test for f??
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Dominance Example
All tests of F2
F1
s-a-1
001 110 010 000 101
100
011
Only test of F1
s-a-1
s-a-1
s-a-1
s-a-0
A dominance collapsed fault set
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Fault Dominance in Sequential Circuits

• Fault dominance is not applicable in seq. circuits

x4
x5
y1 initially
x1
S
y
G1
R
sa1
sa0
x2
z
G2
Test sequence
x3
Fault free output 0000
Faulty response (x2, sa1)0001 Faulty response
(G1 sa0)0000
G1 sa0 dominates x2 sa1
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Structural Equivalance

• Nf the faulty circuit fault f
• Fault f creates a set of lines with constant
  values
• Remove all constant-value lines except POs
• Two faults are structurally equivalent if the
  corresponding simplified circuits S(Nf) and S(Ng)
  are identical.
• Structurally equivalent faults are also
  functionally equivalent

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Structural Equivalence
sa0
sa1
S(Nf)S(Ng)
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Checkpoints

• Primary inputs and fanout branches of a
  combinational circuit are called checkpoints.
• Checkpoint theorem A test set that detects all
  single stuck-at faults on all checkpoints of a
  combinational circuit, also detects all single
  stuck-at faults in that circuit.

Total fault sites 16 Checkpoints ( ) 10
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Classes of Stuck-at Faults

• Following classes of single stuck-at faults are
  identified by fault simulators
• Potentially-detectable fault -- Test produces an
  unknown (X) state at primary output (PO)
  detection is probabilistic, usually with 50
  probability.
• Initialization fault -- Fault prevents
  initialization of the faulty circuit can be
  detected as a potentially-detectable fault.
• Hyperactive fault -- Fault induces much internal
  signal activity without reaching PO.
• Redundant fault -- No test exists for the fault.
• Untestable fault -- Test generator is unable to
  find a test.

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Multiple Stuck-at Faults

• A multiple stuck-at fault means that any set of
  lines is stuck-at some combination of (0,1)
  values.
• The total number of single and multiple stuck-at
  faults in a circuit with k single fault sites is
  3k-1.
• A single fault test can fail to detect the target
  fault if another fault is also present, however,
  such masking of one fault by another is rare.
• Statistically, single fault tests cover a very
  large number of multiple faults.

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Fault Masking

• Let Tg be the set of all tests that detect a
  fault g. Fault f functionally masks the fault g
  iff the multiple fault f,g is not detected by
  any test in Tg
• Let Tg be subset T be the set of all tests in T
  that detect a fault g. We say that a fault f
  masks the fault g under a test T iff the multiple
  fault f,g is not detected by any test in Tg
• Masking relations among different type of faults
  undetectable bridging fault that masks a
  detectable SSF under a complete test set for
  SSFs.

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Functional Masking Example
a
b
c

• 011 is the only test that detects the fault c
  s-a-0 the same test does not detect the multiple
  fault c sa0, a sa1. Fault a masks fault c.

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Fault Masking cont.
a
b
c

• If f masks g, then fault f,g is not detected by
  the tests that detect g alone. But f,g may be
  detected by other vectors. c sa0, a sa1 is
  detected by the test 010.

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Circular Fault Masking Problem

• Given a complete test set T for single faults,
  can there exist a multiple fault Ff1, f2, ,
  fk such that F is not detected by T? (note T
  detects every fi alone)
• Complete Test set T1111,0111,1110,1001,1010,0101
  
• f B sa1, g C sa1
• 1001 is the only test that detects f and g
• Multiple fault f,g is not detected by 1001
  since f masks g and g masks f.

A
B
C
D
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Multiple Line Redundancy

• Circular functional masking relations may result
  in an undetectable multiple fault F
• Example faults f and g are detectable. However,
  f,g is undetectable because f masks g and g
  masks f.
• Circular masking is necessary condition for
  multiple fault F to undetectable but not
  SUFFICIENT!

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Summary

• Fault models are analyzable approximations of
  defects and are essential for a test
  methodology.
• For digital logic single stuck-at fault model
  offers best advantage of tools and experience.
• Many other faults (bridging, stuck-open and
  multiple stuck-at) are largely covered by
  stuck-at fault tests.
• Stuck-short and delay faults and
  technology-dependent faults require special
  tests.
• Memory and analog circuits need other specialized
  fault models and tests.