Differential Amplifier

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Differential Amplifier

• Ramen Dutta
• Research Consultant
• Advance VLSI Design Lab , IITKGP

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Problem in Single-Ended Amplifier

• Bias, gain is Sensitive to Device Parameters
  (µCox,Vt).

• Consider a common source circuit with Gain Req50
• Let Vt1V and Vdd3.3V

• The Transistor is in saturation between Vin
  1V to 1.06V.
• (Across temperature Vt can vary from 0.8V to
  1.2V)
• It is impossible to keep the MOS in saturation in
  full temperature variation

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Problem in Single-Ended Amplifier (cont)

• Sensitive to power supply noise.(due to package
  inductance, cross talk, substrate noise etc).
• Many signal exhibit common mode drift which
  gets amplified.

Symbol for a Differential Amplifier
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Solution Differential Amplifier

• Differential Amplifier A differential amplifier
  is an amplifier that amplifies the difference
  between two voltages and rejects the average or
  common mode value.

• This Solves those issues
• Higher immunity to process, temperature
  variations.
• Higher immunity to supply voltage and
  environmental noise.
• Common mode Rejection avoids the unwanted common
  mode drift.

v1
Symbol for a Differential Amplifier
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Advantages of Differential Signaling

• Higher immunity to process, temperature
  variations.
• Higher immunity to environmental noise.
• Common mode Rejection avoids the unwanted common
  mode drift.
• Less effects to the other lines.
• Increase in maximum voltage swing.
• Simpler biasing and higher linearity.

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Differential Common-mode signals

• Differential-mode input voltage, vID .

• Common-mode input voltage, vIC .

Therefore vID v1 - v2 and vIC
(v1 v2) / 2
So inputs can be represented as ,
v1 VIC VID/2 , v2 VIC VID/2
The output voltage of the differential amplifier
can be expressed in terms of its
differential-mode and common-mode input voltage
as -
Vout AVDvID AVCvIC AVD (v1-v2)
AVC(v1v2)/2
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Basic Structure
vout
M1
M2
vIN2
vIN1
vGS1
vGS2
M3
VBulk

• M1 M2 are source coupled input pair .
  Parameters of both M1 and M2 changes equally. By
  some layout technique, they can be MATCHED
• M3 and M4 are implementation of current sink.
  All transistor should remain in saturation.

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Large Signal Analysis
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• Transconductance Characteristics of the
  Differential Amplifier

Defining Equations vID vGS1-vGS2 (2iD1/b)1/2
- (2iD2/b)1/2 and ISS iD1 iD2
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Small Signal Analysis

• Figure of Merit
• Differential mode voltage gain (required high)

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Small Signal Analysis (cont ..)

• Two steps to simplify the problem
• 1. Use superposition theorem and break into two
  problems.

Differential mode
vid/2
vid/2
2. Exploit symmetry Break the Circuit into Two
Half Circuit.

vo1
vo2
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Differential mode analysis
vo1

• No Voltage Relative to GND along the access of
  Symmetry.

• Analysis of the half circuit is enough. With vo2
  - vo1

• Differential Mode Voltage Gain ,

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Common mode analysis
I0
vo1

• No Current across wires connecting two half
  circuits.

• Analysis of the half circuit is enough. With vo2
  vo1

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Differential Amplifier (Resistive Load)
Differential Mode
Small Signal Analysis Example
VDD
R1
vo1
M1
Differential-mode circuit
General circuit
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Differential Amplifier (Resistive Load) Common
Mode
Small Signal Analysis Example
VDD
R1
vo1
M1
M5/2
Vbias
General circuit
Common mode circuit
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Differential Amplifier (Resistive Load) Common
Mode
Small Signal Analysis Example
Small signal model
CMRR
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High Frequency Analysis
VDD
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Single Ended Out Diff-Amp
VIC(max) VDD VSG3 VTN1
VIC(min) VDS5(sat) VGS1 VDS5(sat) VGS2
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Current mirror load Diff-Amp (cont .)

• small signal gain is inversely proportional to
  the square root of the bias current.

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Slew Rate

• When large signal is applied the MOS transistor
  goes out of the desired operating region.
• Thus the linear properties of the Differential
  amplifier vanishes.
• The maximum current available at the output to
  charge or discharge the load capacitance is Iss
  (the tail current)
• Maximum Rate of Voltage change is called slew
  rate.
• Slew Rate Iss/CL

VDD
R2
R1
vo2
vo1
ISS
v1
V20V
M2
M1
OFF
ISS
M5
Vbias
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• Solved Example Design of a CMOS
  Differential Amplifier with a Current Mirror
  Load

WHAT IS DESIGN ? The design in most CMOS
circuits consists of an architecture represented
by a schematic, W/L values of transistors, and
dc currents which satisfies the specification
given.
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• Design continued

STEPS 1. Choose I5 to satisfy the slew rate
knowing CL or the power dissipation. 2. Check to
see if Rout will satisfy the frequency response,
if not change ISS or modify circuit. 3.
Design W3/L3 (W4/L4) to satisfy the upper
ICMR. 4. Design W1/L1 (W2/L2) to satisfy the
small signal differential gain. 5. Design W5/L5
to satisfy the lower ICMR. 6. Iterate where
necessary.
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• Design continued

Solution
1. Slew rate gives, ISS gt 50mA. Pdiss gives ISS lt
200mA.
2. f-3dB ? Rout lt 318kW. From here and using
Rout2/((lN lP)ISS, we get ISS gt 70mA.
Lets pick ISS 100mA.
3. VIC(max) VDD VSG3 VTN1 gives W3/L3
(W4/L4) 8
4. Av 100V/V gm1Rout ? W1/L1 (W2/L2)
18.4
5. VIC(min) VSS VDS5(sat) VGS1 ? W5/L5
300
6. Since W5/L5 is too large, we should increase
W1/L1 to reduce VGS1 and allow a smaller
W5/L5. If W1/L1 40, then W5/L5 9.
Note Here Av increases to 111.1 V/V, which
should be Okay.
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Other load Structures
Diode Connected MOS (High BW)
Current Source Load (High Gain)
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Other Differential Amplifier Structures
Will be discussed in Operational Amplifier

• THANK YOU