CMOS AMPLIFIERS

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CMOS AMPLIFIERS

• Simple Inverting Amplifier
• Differential Amplifiers
• Cascode Amplifier
• Output Amplifiers
• Summary

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Simple Inverting Amplifiers
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Small Signal Characteristics
Inverter with diode connection load
How do you get better matching?
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High gain inverters
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Current source load or push-pull

• Refer to book for large signal analysis
• Must match quiescent currents in PMOS and NMOS
  transistors
• Wider output swing, especially push-pull
• Much higher gain (at DC), but much lower -3dB
  frequency (vs diode load)
• About the same GB
• Very power dependent

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Small signal
High gain! Especially at low power.
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• Key to analysis by hand
• Use level 1 or 3 model equations
• Use KCL/KVL

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Dependence of Gain upon Bias Current
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Transfer function of a system
input u
output y
System
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When u(s) 0, y(s) satisfies
These dynamics are the characteristic dynamics of
the system. The roots of the coefficient
polynomial are the poles of the system.
When y(s) 0, u(s) satisfies
These dynamics are the zero dynamics of the
system. The roots of the coefficient polynomial
are the zeros of the system.
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Frequency Response of CMOS Inverters
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Poles of CMOS Inverters
Let vin 0, x 0, VDD 0, VSS 0.
CGS1, CGS2, CBS1, CBS2 are all short
y
CGD1, CGD2, CBD1, CBD2, CL in parallel
CL Ctotal CGD1 CGD2 CBD1 CBD2 CL
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Total conductance from y to ground
go gds1 gds2
KCL at node y
Therefore system pole is
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Zeros of CMOS Inverters
Let vin x u, VDD 0, VSS 0.
CGD1, CGD2, are in parallel, CBD1, CBD2, CL are
all short
gds1, gds2 also short
No current in them
KCL
Zero is
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Zeros of CMOS CS Load Amp
Let vin u, X0, VDD 0, VSS 0.
CGS2, CGD2, CBD1, CBD2, CL are all short
gds1, gds2 also short
No current in them
KCL
Zero is
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Input output transfer function
When sjw?0, A(0) ?
When w?8, A(s)?
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-3dB frequency of closed loop bGB
A0 gm/go
Acl1/b
0 dB
p1 g0/CL
Unity gain frequency A0p1 GB gm/CL
z1 gm/Cgd GBCL/Cgd
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Unity gain feedback
A(s)
Closed-loop zero z1
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If a step input is given, the output response is
By the final value theorem
By the initial value theorem
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-1
Final settling determined by A0 ? need high
gain Settling speed determined by A0p1GBUGF, ?
need high gain bandwidth product
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Gain bandwidth product
CL Ctotal CGD1 CGD2 CBD1 CBD2 CL
When CL CL, W??GB?, but it saturates, when
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Note
If VEB1 and VEB2 are fixed, W1/L1 and W2/L2 must
be adjusted proportionally, and they are
proportional to DC power.
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Therefore
P is proportional to W1, W2 CL constant, but
C(W1,W2) proportional to W1, W2 When C(W1, W2) ltlt
CL, GB proportional to P When C(W1,W2)?CL or gtCL,
GB saturates
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GB
Linear increase region
P
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For given current or power (current source load)
Initially, as W1 increased, GB increases But GB
will reach a max, and then drop as W1 increases
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NOISE IN MOS INVERTERS
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To minimize

1. L2 gtgtL1
2. En1 small

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For thermal noise
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Noise in Push-Pull current source load Inverter
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Differential Input, single-ended output single
stage Amplifier
N-Channel
vin-
vin
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P-channel
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Large Signal Eq. in a N-channel Differential pair
0.5b1(VGS1-VT)2
(2ID1/b1)0.5
iD10, when iD2ISS and VGS2VT(2ISS/b)0.5
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Solving for iD1 and iD2
VON1VON2(ISS/b)0.5
iD1iD2ISS/2
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N-Channel Input Pair Differential Amplifier
C.M. Load
Simple current reference
C.M. Bias
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Voltage transfer curve
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P-Channel Input Pair Differential Amplifier
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Voltage transfer curve
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INPUT COMMON MODE RANGE
VG1VG2ViCM
VSDSAT1VSDSAT2 VON
VD1VD3 VSSVT3VON
VG1minVD1-VT1
VG1maxVDD- VSD5SAT-VT1-VON
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Output Range
VominVssVon4
VomaxVicm VT2
So whats the vo range
Whats for the N-ch circuit.
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SMALL SIGNAL ANALYSIS
AV
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Common Mode Equivalent Circuit, with perfect
match
iC1VIC/(1/gm1 2rds5)
ro11/gm3
ACM 1/ 2rds5gm3
iC1
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If not perfectly matched
ioaiIC a is a fraction
go1 gds4 gds2/2Av5 gds4
iC1
ACM agm5 / 2gds4
CMRRAv/ACM gm1/agm5
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Formal detailed analysis
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SLEW RATE the limit of the rate of change of
the output voltage
CLdvo/dti4-i2
Max CLdvo/dtISS
ISS
ISS
Slew Rate ISS/CL
0
ISS
Output swing Vosw GB frequency
fGB vo(t)Voswsin(2pfGBt) Max dvo/dt
Vosw2pfGB
To avoid slewing ISS gt CL Vosw2pfGB
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Parasitic Capacitances
CT common mode only
CM mirror cap Cdg1 Cdb1 Cgs3 Cgs4
Cdb3
COUT output cap Cbd4 Cbd2 Cgd2 CL
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• Impedances
• rout rsd2 rds4 1 / (gds2 gds4)
• rM 1/gm3 rds3 rds1 1/ gm3
• Hence the output node is the high impedance node
• When vi0, slowest discharging node is output
  node with dominant pole p1 -1/(Coutrout),
  where Cout Cout Cgd4
• Approximate transfer function
• AV(s) AV/(s/p1-1)

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When vG1vG20(AC)
KCL at D1
KCL at D2
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Gain bandwidth product

• Gain AV(0) gm1 / (gds2 gds4)
• Bandwidth p1 (gds2 gds4) / Cout
• GBW gm1 / Cout
• gm1 2ID1mCoxW1/L1½
• increase gm1 ? increase GBW
• increase W1 ? increase GBW
• But Cout has Cdb2 and Cgd2 ? W1
• Once Cdb2 and Cgd2 become comparable to CL,
  increasing W1 reduces GBW

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Other poles and zeros
VDD
Second pole at D1

r 1/gm3
M3
M4
C CM
VOUT
(1AV4)Cgd4
(1AV4)Cgd4
CL
Cgd4
AV4 gm4/gds4
M2
M1
Vi
Vi-
- gm3
p2
M5
Vb2
CM (1AV4)Cgd4
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Unstable zero at Cgd2
Enforce vo0, float vin.
ids2, ids4 0
Cgd2 dvi-/dt gm2 vi-
z1 gm2/Cgd2
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VDD
For zero at D1
For diff, Vi - Vi-

M3
M4
which is set by Cgd2
VOUT
?Both Cgd4 and Cgd1 to gnd
CL
Ctot CM Cgd4
M2
M1
Vi
Vi-
-gm3
z2
CM Cgd4
M5
Vb2
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• A better approximation of TF AV(s)AV(s/z1-1)(s
  /z2-1)/(s/p1-1)(s/p2-1)
• If p1 is dominant, p1ltltp2,z1,z2
  AV(s)AV/(s/p1-1)
• If p1 is non-dominant, at low frequency,
  AV(s)AV /(s/p1s/p2-s/z1-s/z2 -1)
• 1/peq 1/p11/p2-1/z1-1/z2
  1/p11/p2-1/z2 , since z1 gtgt z2, p1, p2
  1/p1, if AV4 is not very large
• In either case, BW p1

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frequency response
AV
All in abs val
z1
w
p1
p2
z2
UGF
-90
PM
-180
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Observations

• PM 90 tan-1(UGF/z1)
• GBW should be at least 23 times lower than z1 to
  ensure good phase margin at UGF
• There is conflict between AV and PM
• If z2 not p2, UGF lt AVp1
• Design approaches
• make z1 high ? higher than UGF
• make Cgd2 small, gm1 large
• make z2 close to p2 ? better 1st order approx.
• make AV4 small
• make p1 low ? large AV
• make gds2 and gds4 small

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Design Steps

• Select Iss based on
• GB V_osw, SR, or P_max
• Select W1/L1 based on
• GB gm/CL, Assuming CL (1.11.5)CL
• Maximize z1 (minimize Cgd2)
• Select W4/L4 based on
• ICMR,
• Small Av4
• Select W5/L5 based on
• ICMR

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NOISE Model
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Input equivalent noise source
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• Total output noise current is found as,
• Let
• Then

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How does this affect Av4 and go?
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Cascoding

• Objectives
• Increase ro
• Increase AV
• Remove feed forward from vin to vo
• Remove unstable zero
• Methods
• Direct cascoding
• Folded cascoding

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CMOS CASCODE AMPLIFIERS
Vout-min increase by VON2 Vout-max decreased if
a Cascoded source used Output swing is a big
Problem in low voltage Applications
Rb
Vin
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Cascoded current source load
Q How should you set the bias? Q what is
Vout-max?
ro
AV
ro at D1?
vD1 vin

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High frequency model
AV0(s/z1 -1)
AV(s)
(s/p1-1)(s/p2-1)
Consider only the effect of the lower half
circuit.
For poles, short input, and compute the time
constants at each node. For zeros, float input
but require vo 0. (dont short vo!)
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Short vin, float vo
At the high impedance node
r rds1(gm2gmb2)rds2
C CLCdb2Cgd2
p1 -1/RC
At the low impedance node
r 1/(gm2gmb2gds1gds2)
C Cgd1Cdb1Cgs2Csb2
p2
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Enforce vo0, float vin.

• iCo0, no current cross line, and iCgd20
• id2, id3 0, gm2vgs20

At the G1-D node
igds10
sCgd1vingm1vin
vs20
Was the unstable zero removed?
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Gain bandwidth product

• If p1 ltlt p2, p3,, p1 ltlt z1, z2,
• BW p1
• GBW gm1/Co
• Otherwise
• AV(s) AV/(s/p1s/p2-s/z1-s/z2 - 1)
• 1/BW 1/p12/p2-1/z1-2/z2 RC1 RC2

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Any enhancement?
Note rds2, Rb ? 1/ID2
gm2 ? vID2
Effects on ro, AV Co, GBW Slew rate
Rb
Vbb
Vin
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Another possible modification
Effects on ro, AV? Co, GBW? Slew
rate? poles? zeros?
Rb
Vbb
Vin
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Folded cascoding
Which I source should be cascoded? ro, AV? Co,
GBW? Slew rate? poles? zeros?
Vbb
Vin
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OUTPUT AMPLIFIERS

• Requirements
• Provide sufficient output power in the form of
  voltage or current.
• Avoid signal distortion for large signal swings.
• Be power efficient.
• Provide protection from abnormal conditions.
• Types of Output Stages
• Class A amplifier.
• Source follower.
• Push-Pull amplifier ( inverting and follower).
• Negative feedback (OP amp and resistive).

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Power efficiency

• It is most power efficient at maximum signal
  level
• Let VSS -VDD, Vin is sinusoidal such that Vout
  reaches Voutmax
• PRL ½ (Voutmax)2/RL
• Psupplygtaverage((VDD or VSS)IRL)
  VDDaverage(Voutmaxsin()/RL)
  2VDDVoutmax/RL/p
• Power efficicy PRL/Psupplyltp/4 (78)

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CLASS A AMPLIFIER
ro, AV, z, p as before
PRL
Power effic
Psupply
0.5voutmaxIQ
lt 25

IQ(VDD-VSS)
VSS -VDD, VoutmaxVDD-Vdssat
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SOURCE FOLLOWER
or VSSVT
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Push-pull
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Push-pull inverting amp
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Implementation
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PUSH-PULL SOURCE FOLLOWER
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If Vo 0
Bias current well controlled
Vo swing is very limited
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If A(Vosp-Vosn)ltltVov
If VospVosn0
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Combining the previous two
At quiescent, Vov1vgs4-vgs1v1 This
requires (W/L)1W/L)2 (W/L)4W/L)5
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Example error amplifier
M15 is like a resistor connecting the drain and
gate of M17, leaving M17 as level shifted diode
connection. ?I17 Ib. By CM connection, I13 I14
mIb. I11I12Itail/2. I15I16I13-I12mIb-It/2
. When vi ! vo, I12 varies from 0 to Itail.
Hence, need mIb gt Itail.
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Super source follower

• DVo gt DI1 (gm1gmb1)DVo
• DVGS2 ro1(gm1gmb1)DVo
• DI2 gm2ro1(gm1gmb1)DVo

I1
gogm2ro1(gm1gmb1) (gm1gmb1)go2
gm2ro1(gm1gmb1)
Vo
Vin
Gm gm1gm1ro1gm2
I2
gm1
AVGm/go
gm1 gmb1
Ex rework these when I1 and I2 have finite ros.
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If we re-arrange with a flipped version, we get
this push-pull super source follower
I1
Vo
Vin
Ex provide a transistor level implementation. Com
ment on power efficiency.
I2
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