MIPS Operation

1
MIPS Operation

• J.Ainscough
• Computer Systems Group
• Manchester Metropolitan University
• J.Ainscough_at_mmu.ac.uk

2
Introduction
The next slide shows the complete circuit diagram
for a simple implementation of the MIPS
Processor described in Computer Organisation and
Design The hardware/ software interface By
Patterson and Hennessy
The animation will show how the various
components are activated in order to execution
the various instruction types described in the
above text.
3
(No Transcript)
4
Instruction Fetch Phase
The instruction is fetched from the
instruction memory and the program counter is set
to point to the next instruction
5
Concatenate a, b
Jump Address31-0
Instruction25-0
Instruction31-28
ADD2
RegDst
ADD1
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Register 1
Read Data 1
Instruction25-21
Instruction20-16
Read Register 2
Read Data 2
0
Write Register
Registers
MUX1
Write Data
1
Instruction15-11
Instruction Bus
Instruction15-0
Instruction5-0
The Program Counter (PC) addresses the
Instruction Memory which in turn delivers an
instruction to the Instruction Bus
6
Instruction Decode Phase 1
The op-code parts of the instruction is
examined by the control logic and the correct
control signals are generated and used to
activate the required elements of the data
path. The register addresses and the other
fields are extracted directly from the
instruction.
7
Concatenate a, b
Jump Address31-0
Instruction25-0
Instruction31-28
ADD2
RegDst
ADD1
Jump
Branch
MemRead
Control
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Register 1
Read Address
Read Data 1
Instruction31-0
Read Register 2
PC
Read Data 2
Instruction Memory
0
Write Register
Registers
MUX1
Write Data
1
Sign Extend
The instruction is split into several groups
(fields) which correspond to the format of the
groups of bits in the various types of instruction
8
Instruction Decode Phase 2 Next Address
Generation Control signals
9
Concatenate a, b
1
MUX5
Jump Address31-0
Instruction25-0
0
Instruction31-28
ADD2
RegDst
ADD1
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Register 1
Read Address
Read Data 1
Instruction25-21
Instruction31-0
Instruction20-16
Read Register 2
PC
Read Data 2
Instruction Memory
0
Write Register
Registers
MUX1
Write Data
1
Instruction15-11
Sign Extend
Instruction15-0
Instruction5-0
The instruction bits31-26 are used to activate
Control signals. Here the control signals
associated with the next address generation are
activated
10
Data Path for Next Address Generation
11
Concatenate a, b
Jump Address31-0
Instruction25-0
Instruction31-28
ADD2
RegDst
Gate
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Register 1
Read Address
Read Data 1
Instruction25-21
Instruction31-0
Instruction20-16
Read Register 2
PC
Read Data 2
Instruction Memory
0
Write Register
Registers
MUX1
Write Data
1
Instruction15-11
Sign Extend
Instruction15-0
Instruction5-0
The PC is fed through Add 1 and 4 is added to it
to accommodate the byte addressing of MIPS the
result is then route back to the PC register.
12

• The Execute Phase
• The previous operations Fetch and Decode are
• common to operation several types of instruction.
  
• The following slides show the particular
  behaviour of
• Type R instructions
• Type I instructions (load store)
• N.B In the following sequence the control
  signals are colour coded GREEN implies a logic0
  and RED implies a logic 1 BLUE indicates the
  ALU control signals are active.

13
Control Signals activation for the Data Path
configuration for a Type R Instruction
14
Concatenate a, b
1
MUX5
Jump Address31-0
Instruction25-0
0
MUX4
0
Instruction31-28
1
ADD2
RegDst
ADD1
Gate
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Register 1
Read Address
Read Data 1
Instruction25-21
Instruction31-0
Instruction20-16
Read Register 2
PC
Read Data 2
Instruction Memory
0
Write Register
Registers
MUX1
Write Data
1
Instruction15-11
Sign Extend
Instruction15-0
Instruction5-0
The control logic generates the control signals
to activate the parts of the data path that are
required to implement a type R instruction
15
Activation of Data Path for a Type R Instruction
16
Concatenate a, b
1
MUX5
Jump Address31-0
Instruction25-0
0
MUX4
0
Instruction31-28
1
ADD2
RegDst
ADD1
Gate
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Address
Instruction25-21
Instruction31-0
Instruction20-16
PC
Instruction Memory
Instruction15-11
Sign Extend
Instruction15-0
Instruction5-0
The register file address are derive from fields
in the instruction. The output of multiplexers is
determined by the logic level on the control
signal. The ALU function is controlled the values
of the signals on the input of ALU control
17
Control Signals activation for the Data Path
configuration for a Type I Instruction (In this
case a load instruction)
18
Concatenate a, b
1
MUX5
Jump Address31-0
Instruction25-0
0
MUX4
0
Instruction31-28
1
ADD2
RegDst
ADD1
Gate
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Register 1
Read Address
Read Data 1
Instruction25-21
Instruction31-0
Instruction20-16
Read Register 2
PC
Read Data 2
Instruction Memory
0
Write Register
Registers
MUX1
Write Data
1
Instruction15-11
Sign Extend
Instruction15-0
Instruction5-0
The control logic generates the control signals
to activate the parts of the data path that are
required to implement a type I instruction (load)
19
Activation of Data Path for a Type I
Instruction (load)
20
Concatenate a, b
1
MUX5
Jump Address31-0
Instruction25-0
0
MUX4
0
Instruction31-28
1
ADD2
RegDst
ADD1
Gate
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Address
Instruction25-21
Instruction31-0
Instruction20-16
PC
Instruction Memory
0
MUX1
1
Instruction15-11
Sign Extend
Instruction15-0
Instruction5-0
The data path that are required to implement a
type I instruction(load)
21
Control Signals activation for the Data Path
configuration for a Type I Instruction (In this
case a store instruction)
22
Concatenate a, b
1
MUX5
Jump Address31-0
Instruction25-0
0
MUX4
0
Instruction31-28
1
ADD2
RegDst
ADD1
Gate
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Register 1
Read Address
Read Data 1
Instruction25-21
Instruction31-0
Instruction20-16
Read Register 2
PC
Read Data 2
Instruction Memory
0
Write Register
Registers
MUX1
Write Data
1
Instruction15-11
Sign Extend
Instruction15-0
Instruction5-0
The control logic generates the control signals
to activate the parts of the data path that are
required to implement a type I instruction (store)
23
Activation of Data Path for a Type I
Instruction (store)
24
Concatenate a, b
1
MUX5
Jump Address31-0
Instruction25-0
0
MUX4
0
Instruction31-28
1
ADD2
RegDst
ADD1
Gate
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Address
Instruction25-21
Instruction31-0
Instruction20-16
PC
Instruction Memory
0
MUX1
1
Instruction15-11
Instruction15-0
Instruction5-0
The data path that are required to implement a
type I instruction (store)
25
Control Signals activation for the Data Path
configuration for a Type I Instruction (In this
case a branch if equals instruction) The
instruction first determines the result of the
Branch Condition by reading the values of
the registers into the ALU and then setting ZERO
To the appropriate value
26
Concatenate a, b
1
MUX5
Jump Address31-0
Instruction25-0
0
MUX4
0
Instruction31-28
1
ADD2
RegDst
ADD1
Gate
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Address
Instruction25-21
Instruction31-0
Instruction20-16
PC
Instruction Memory
Instruction15-11
Sign Extend
Instruction15-0
Instruction5-0
The control logic and the ALU generate the
control signals to activate the parts of the data
path that are required to implement a type I
instruction (beq)
27
Data Path for Next Address Generation
The next address can now be computed using the
address data path set by the control signal.
Here it will be assumed that the branch is to
be taken
28
Concatenate a, b
Jump Address31-0
Instruction25-0
Instruction31-28
RegDst
ADD1
Gate
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Address
Instruction25-21
Instruction31-0
Instruction20-16
PC
Instruction Memory
0
MUX1
1
Instruction15-11
Instruction15-0
Instruction5-0
The sign extended branch offset address is now
added to the Program Counter to give the target
address.
29
Control Signals activation for the Data Path
configuration for a Type J Instruction
30
Concatenate a, b
Jump Address31-0
Instruction25-0
Instruction31-28
ADD2
RegDst
ADD1
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Register 1
Read Data 1
Instruction25-21
Instruction20-16
Read Register 2
Read Data 2
0
Write Register
Registers
MUX1
Write Data
1
Instruction15-11
Instruction15-0
Instruction5-0
The only active control signal is jump which
selects the 1 inout from mux 5
31
Data Path for Jump Target Address Generation
32
Concatenate a, b
Jump Address31-0
Instruction25-0
Instruction31-28
ADD2
RegDst
Jump
Branch
MemRead
Control
Instruction31-26
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read Register 1
Read Data 1
Instruction25-21
Instruction20-16
Read Register 2
Read Data 2
0
Write Register
Registers
MUX1
Write Data
1
Instruction15-11
Instruction15-0
Instruction5-0
The upper 4 bits of the Program Counter (PC4)
are concatenated with the lower 26 bits of the
instruction shifted 2 bits to the left
33
The end of the presentation

• J.Ainscough