Chapter%203%20-%20Digital%20Logic%20Level

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Chapter 3 - Digital Logic Level

• Gates
• Basic Digital Logic
• Memory
• Storage Hierarchy
• CPU
• PII
• PicoJava
• Bus
• PCI
• Homework
• Chapter 3 1, 4, 6, 12, 25, 35, 37, 40 (Due 4/22)

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Gates and Boolean Algebra

• X !A

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Functions
_ _ _ MABCABCABCABC M (!A) B
C A (!B) C A B (!C)
A B C
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Completeness of NAND and NOR
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Equivalence and Minimization

• XXYY XY

6
Identities for formula transform
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Transforming formulas
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0-60 in 4.2 sec.
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Memory

• SR Latch

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Clocked latches

• Clocked SR latch
• Clocked D latch

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Clocking
12
D Flip-Flop
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4 x 3 (3?)
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Simple Bus
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Dynamic RAM
16
CPU chip I
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Buses Everywhere!
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Bus overview

• P IV (.013 micron)
• 36 addr lines
• 64 data lines
• MANY control lines

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Synchronous bus overview
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Bus arbitration
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P II cpu bus

• 33 ADDR
• 64 Data
• Bus pipeline
• Arbitration
• Request
• Error
• Snoop
• Response
• Data

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PicoJava

• Built-in ram/PROM bus
• Built-in PCI bus support
• 16 Built-in I/O lines

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A real bus - PCI
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PCI - more