8 bit Microprocessor Design

1
8 bit Microprocessor Design

• Dereck Fernandes
• Priyank Kalla

2
Status Summary

• RTL Description in Verilog Completed.
• Functional Testing Done.

3
Memory Design

Datamemory.v
Clock
(72bytes)
//Read Dout MEMAddress //Write if
(WE1) MEMAddress lt Din
Address
Data Out
Data IN
Write Enable
4
ALU Design
Alu.v

30 Operation
70 Result
ADD A B SUB A - B AND A B OR A
B XOR A B COM A ROR CIN,A71 ROL
A60,CIN SWAP A30,A74
70 Input A
Carry out
70 Input B
Zero Flag
Carry In
5
Instruction Decoder Design
Idecoder.v

10 Select ALU A Input (W, SBUS, K)
10 Select ALU B Input
// RLF f,d // 0011 01df ffff 12 bit OpCode //
Carry Flag is affected 12b0011_010X_XXXX decode
s 12b01_01_0110_1_0_0_1
110 Instruction
30 ALU Operation
Write Enable Register W
Write Enable File Register
Write Enable Bit Zero
Write Enable Bit Carry
6
CPU Control Design
CPU.v

Program Memory Address
Clock
110 Inst 100 PC 100 stack1,
stack2 70 W 70 status // bit0 -C, bit2 -
Z 70 sbus // Instantiate ALU, REGS, IDEC
Reset
Debug W
Debug PC
Program Memory Data
Debug INST
Debug Status
7
Test Bench Design

// Create a Clock // Reset Pin // Write a ROM
file // Instantiate CPU.v // Monitor // W //
INST // STATUS
8
Results

• ROM Address 0ed, Data cf8 //1100 1111 1000
• ROM Address 0ee, Data FAA //0010 0000 0101
• MONITOR_INST 0ed MOVF 5(0x05), W
• MONITOR_INST 0ee XORLW 170(0xaa)
• W aa
• SUCCESS.
• End of simulation signalled. Killing simulation
  in a moment.
• L255 "test.v" finish at simulation time 26411
• 0 simulation events (use profile or listcounts
  option to count)
• CPU time 0.3 secs to compile 0.1 secs to link
  2.6 secs in simulation
• End of VERILOG-XL 3.11.s007 Mar 29, 2002
  110821

9
Goals for Next Review

• By April 15, 2002.
• Validation Complete Testbenches
• Logic Synthesis, technology mapping, placement
  and routing.
• Area/performance analyses
• -- LUT-depth
• --Number of LUTs
• --Timing Specification (20 MHz).